The V96BMC Revision D Burst DRAM Controller is an enhanced version of the previous V96BMC with improved timing and provides dedicated Power and Ground rails to support the increasingly popular 3.3V DRAM modules. Timing parameters are also improved over the older versions of the device.
The V96BMC provides the DRAM access protocols, buffer signals, data multiplexer signals, and bus timing resources required to work with DRAM. By using the V96BMC, system designers can replace tedious design work, expensive FPGAs and valuable board space with a single, high-performance, easily configured device. The processor interface of the V96BMC implements the bus protocol of the i960Cx/Hx/Jx. The pin naming convention has been duplicated on the V96BMC; simply wire like-named pins together to create the interface.

• Pin/Software compatible with earlier V96BMC.
• Direct interfaces to i960Cx/Hx/Jx processors.
• 3.3V DRAM interface support.
• Near SRAM performance achieved with DRAM.
• Supports up to 512Mb of DRAM.
• Interleaved or non-interleaved operation.
• Supports symmetric and non-symmetric arrays.
• Software-configured operational parameters.
• Integrated Page Cache Management.
• 2Kbyte burst transaction support.
• On chip memory address multiplexer/drivers.
• Two 24-bit timers, 8-bit bus watch timer.
• Up to 40MHz operation.
• Low cost 132-pin PQFP package.