Functional Description
The CY7C4255/65/65A are high speed, low power, first-in first-out (FIFO) memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to the CY7C42X5 Synchronous FIFO family. The CY7C4255/65/65A can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high speed data acquisition, multiprocessor interfaces, and communications buffering.

FEATUREs
■ High Speed, Low Power, First-In First-Out (FIFO) Memories
   ❐ 8K x 18 (CY7C4255)
   ❐ 16K x 18 (CY7C4265/4265A)[1]
■ 0.5 Micron CMOS for Optimum Speed and Power
■ High Speed 100 MHz Operation (10 ns read/write cycle times)
■ Low Power — ICC = 45 mA
■ Fully Asynchronous and Simultaneous Read and Write Operation
■ Empty, Full, Half Full, and Programmable Almost Empty and Almost Full Status Flags
■ TTL compatible
■ Retransmit Function
■ Output Enable (OE) Pins
■ Independent Read and Write Enable Pins
■ Center Power and Ground Pins for Reduced Noise
■ Supports Free-running 50 percent Duty Cycle Clock Inputs
■ Width and Depth Expansion Capability
■ 64-pin TQFP and 64-pin STQFP
■ Pin-compatible Density Upgrade to CY7C42X5 Family
■ Pin-compatible Density Upgrade to IDT72205/15/25/35/45
■ Pb-free Packages Available