CY7C4255-15AC(2004) 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C4255-15AC Datasheet PDF : 22 Pages
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Pin Configurations
TQFP/STQFP
Top View
CY7C4255
CY7C4265
D15
1
D14
2
D13
3
D12
4
D11
5
D10
6
D9
7
D8
8
D7
9
D6
10
D5
11
D4
12
D3
13
D2
14
D1
15
D0
16
CY7C4255
CY7C4265
48
Q14
47
Q13
46
GND
45
Q12
44
Q11
43
VCC
42
Q10
41
Q9
40
GND
39
Q8
38
Q7
37
Q6
36
Q5
35
GND
34
Q4
33
VCC
4255–3
Functional Description (continued)
The CY7C4255/65 provides five status pins. These pins are decod-
ed to determine one of five states: Empty, Almost Empty, Half Full,
Almost Full, and Full. The Half Full flag shares the WXO pin. This flag
is valid in the stand-alone and width-expansion configurations. In
the depth expansion, this pin provides the expansion out
(WXO) information that is used to signal the next FIFO
when it will be activated.
Selection Guide
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Active Power Supply
Current (ICC1) (mA)
Commercial
Industrial
7C4255/65-10
100
8
10
3
0.5
8
45
50
Density
Package
CY7C4255
CY7C4265
8K x 18
16K x18
64-pin TQFP, STQFP 64-pin TQFP, STQFP
The Empty and Full flags are synchronous, i.e., they change
state relative to either the Read Clock (RCLK) or the Write
Clock (WCLK). When entering or exiting the Empty states, the
flag is updated exclusively by the RCLK. The flag denoting Full
states is updated exclusively by WCLK. The synchronous flag
architecture guarantees that the flags will remain valid from
one clock cycle to the next. The Almost Empty/Almost Full
flags become synchronous if the VCC/SMODE is tied to VSS.
All configurations are fabricated using an advanced 0.5µ
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
7C4255/65-15
66.7
10
15
4
1
10
45
50
7C4255/65-25
40
15
25
6
1
15
45
50
7C4255/65-35
28.6
20
35
7
2
20
45
50
Document #: 38-06004 Rev. *B
Page 2 of 22
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