CP707(2002) 데이터시트 - Central Semiconductor
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CP707
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Central Semiconductor
PROCESS DETAILS
Process EPITAXIAL PLANAR
Die Size 27 x 27 MILS
Die Thickness 9.0 MILS
Base Bonding Pad Area 5.3 x 3.8 MILS
Emitter Bonding Pad Area 5.3 x 6.5 MILS
Top Side Metalization Al - 30,000Å
Back Side Metalization Au - 18,000Å
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Small Signal Transistor NPN - Silicon Darlington Transistor Chip ( Rev : 2002 )
Central Semiconductor
Small Signal Transistor NPN - High Voltage Darlington Transistor Chip
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