BR24G64NUX-5(2017) 데이터 시트보기 (PDF) - ROHM Semiconductor

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BR24G64NUX-5
(Rev.:2017)

Serial EEPROM Series Standard EEPROM I2C BUS EEPROM (2-Wire)

ROHM Semiconductor 

BR24G64xxx-5 Series

Method of Reset

This IC can be reset by sending the stop condition after executing the start condition. Please execute it when it is necessary

to reset after power-up, or during command input timing. However, the start condition and stop condition could not be

applied because 'HIGH' input of microcontroller and 'LOW' output of EEPROM collide when EEPROM is 'LOW' in ACK

output section and data reading. In that case, input SCL clock until SDA bus is released ('HIGH' by pull-up). After confirming

that SDA is released, send the stop condition after inputting the start condition. If SDA bus could not be confirmed whether

released or not in microcontroller, input the software reset. If software reset is run, EEPROM can be reset without

confirming the SDA state because SDA bus is always released in either of the two start conditions. The method of reset is

shown in the table below.

Status of SDA

Method of reset

SDA bus released

('HIGH' by pull-up)

Send the stop condition after executing the start condition.

'LOW'

Microcontroller cannot

confirm SDA bus is

released or not

Input SCL clock until SDA bus is released, confirm that SDA bus is released, and send the

stop condition after inputting start condition.

Using the software reset shown in the figure below, the start condition can be always

excuted. Within the dummy clock input area, the SDA bus is needed to be released ('HIGH'

by pull-up). For normal commands, start with the start condition input.

SCL

SDA

Start

Dummy clock×9

12

8

Start Stop

9

Normal command

Normal command

Figure 47. Input timing of software reset

Acknowledge Polling

During internal write execution, all input commands are ignored, therefore ACK is not returned. During internal automatic

write execution after write input, next command (slave address) is sent. If the first ACK signal sends back 'LOW', then it

means end of write operation, else 'HIGH' is returned, which means writing is still in progress. By the use of acknowledge

polling, next command can be executed without waiting for tWR = 5ms.

To write continuously, slave address with R / W = 0, then to carry out current read after write, slave address with R / W = 1

is sent. If ACK signal sends back 'LOW', then execute word address input and data output and so forth.

First write command

During internal write,

ACK = HIGH is returned.

START

STOP START

START

Write Command

Slave

Address

Slave

···

Address

ACK

tWR

=HIGH

ACK

=HIGH

START

···

Slave

Address

ACK

tWR =HIGH

Second write command

START

STOP

Slave

Address

Word

Address

Data

ACK

=LOW

ACK

=LOW

ACK

=LOW

After completion of internal write,

ACK=LOW is returned, so input next

word address and data in succession.

Figure 48. The Case of Continuous Write by Acknowledge Polling

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TSZ02201-0GGG0G100910-1-2

30.Nov.2017 Rev.001

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