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BR24G64NUX-5(2017) 데이터 시트보기 (PDF) - ROHM Semiconductor

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BR24G64NUX-5
(Rev.:2017)
ROHM
ROHM Semiconductor ROHM
BR24G64NUX-5 Datasheet PDF : 38 Pages
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BR24G64xxx-5 Series
WP Valid Timing (Write Cancel)
WP is usually fixed to 'HIGH' or 'LOW', but when WP is controlled and used for write cancel and so on, pay attention to the
following WP valid timing. Write can be cancelled by setting WP='HIGH' while it is executed and in WP valid area. In both
byte write and page write, the area from the first start condition of command to the rise of clock which take in D0 of data(in
page write, the first byte data) is the WP invalid area. WP input in this area becomes Don't care. The area from the rise of
clock to take in D0 to the stop condition input is the WP valid area. Furthermore, after the execution of forced end by WP,
the IC enters standby status.
·Rise of D0 taken clock
·Rise of SDA
SCL
SDA
D1 D0 ACK
Enlarged view
SCL
SDA D0 ACK
Enlarged view
START
SDA
Slave
Word
Address Address
D7 D6 D5 D4 D3 D2 D1 D0
Data
STOP
tWR
ACK ACK
=LOW =LOW
ACK
=LOW
ACK
=LOW
WP Invalid Area
WP
WP Valid Area
WP Invalid Area
If WP='HIGH' in this area,
data is not written
Figure 49. WP Valid Timing
Command Cancel by Start Condition and Stop Condition
During command input, by continuously inputting start condition and stop condition, command can be cancelled. However,
within ACK output area and during data read, SDA bus may output 'LOW'. In this case, start condition and stop condition
cannot be inputted, so reset is not available. Therefore, execution of reset is needed referring Method of Reset. When
command is cancelled by start-stop condition during random read, sequential read, or current read, internal setting address
is not determined. Therefore, it is not possible to carry out current read in succession. To carry out read in succession, carry
out random read.
SCL
SDA
1
0
1
0
Start Condition Stop Condition
Figure 50. The Case of Cancel by Start, Stop Condition during Slave Address Input
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30.Nov.2017 Rev.001

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