BR24G64NUX-5(2017) 데이터 시트보기 (PDF) - ROHM Semiconductor

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BR24G64NUX-5
(Rev.:2017)

Serial EEPROM Series Standard EEPROM I2C BUS EEPROM (2-Wire)

ROHM Semiconductor 

BR24G64xxx-5 Series

I2C BUS Communication

1. I2C BUS Data Communication

(1) I2C BUS data communication begins with start condition input, and ends at the stop condition input.

(2) The data is always 8bit long, and acknowledge is always required after each byte.

(3) I2C BUS data communication with several devices connected to the BUS is possible by connecting with 2

communication lines: serial data (SDA) and serial clock (SCL).

(4) Among the devices, there is a “master” that generates clock and control communication start and end. The rest

become “slave” which are controlled by an address peculiar to each device. EEPROM is a “slave”.

(5) The device that outputs data to the bus during data communication is called “transmitter”, and the device that

receives data is called “receiver”.

SDA

1 to 7

8

9

1 to 7

8

9

1 to 7

8

9

SCL

S

START ADDRESS R/W ACK

DATA

ACK

DATA

P

ACK STOP

condition

condition

Figure 40. Data Transfer Timing

2. Start Condition (Start Bit Recognition)

(1) Before executing each command, start condition (start bit) where SDA goes down from 'HIGH' to 'LOW' while SCL

is 'HIGH' is necessary.

(2) This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition

is satisfied, any command cannot be executed.

3. Stop Condition (Stop Bit Recognition)

Each command can be ended by a stop condition (stop bit) where SDA goes from 'LOW' to 'HIGH' while SCL is

'HIGH'.

4. Acknowledge (ACK) Signal

(1) This acknowledge (ACK) signal is a software rule to indicate whether or not data transfer was performed normally.

In both master and slave communication, the device at the transmitter (sending) side releases the bus after

outputting 8-bit data. When a slave address of a write command or a read command is input, microcontroller is the

device at the transmitter side. When data output for a read command, this IC is the device at the transmitter side.

(2) The device on the receiver (receiving) side sets SDA 'LOW' during the 9th clock cycle, and outputs an ACK signal

showing that the 8-bit data has been received. When a slave address of a write command or a read command is

input, this IC is the device at the receiver side. When data output for a read command, microcontroller is the device

at the receiver side.

(3) This IC, after recognizing start condition and slave address (8bit), outputs ACK signal 'LOW'.

(4) Each write operation outputs ACK signal 'LOW' every 8bit data (a word address and write data) reception.

(5) During read operation, this IC outputs 8bit data (read data) and detects the ACK signal 'LOW'. When ACK signal is

detected, and no stop condition is sent from the master (microcontroller) side, this IC will continue to output data. If

the ACK signal is not detected, this IC stops data transfer, recognizes the stop condition (stop bit), and ends the

read operation. Then this IC becomes ready for another transmission.

5. Device Addressing

(1) From the master, input the slave address after the start condition.

(2) The significant 4 bits of slave address are used for recognizing a device type.

The device code of this IC is fixed to '1010'.

(3) The next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and multiple devices can be used

on a same bus according to the number of device addresses. It is possible to select and operate only device whose

'VCC' 'GND' input conditions of the A0, A1, A2 pin match the 'HIGH' 'LOW' input conditions of slave address sent

from the master.

(4) The least significant bit ( R / W --- READ/ WRITE ) of slave address is used for designating write or read operation,

and is as shown below.

Setting R / W to 0 ------- write (setting 0 to word address setting of random read)

Setting R / W to 1 ------- read

Slave address

1 0 1 0 A2 A1 A0 R / W

Maximum number of

Connected buses

8

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© 2017 ROHM Co., Ltd. All rights reserved.

TSZ22111 • 15 • 001

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TSZ02201-0GGG0G100910-1-2

30.Nov.2017 Rev.001

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