MAX192ACAP 데이터 시트보기 (PDF) - Maxim Integrated

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MAX192ACAP

Low-Power, 8-Channel,Serial 10-Bit ADC

Maxim Integrated 

Low-Power, 8-Channel,

Serial 10-Bit ADC

+5V

510k

100k

MAX192

REFADJ

12

0.01µF

24k

Figure 17. Reference-Adjust Circuit

SUPPLIES

+5V

GND

R* = 10Ω

VDD

AGND

DGND

+5V DGND

MAX192

DIGITAL

CIRCUITRY

* OPTIONAL

Figure 18. Power-Supply Grounding Connection

Layout, Grounding, Bypassing

For best performance, use printed circuit boards.

Wire-wrap boards are not recommended. Board layout

should ensure that digital and analog signal lines are

separated from each other. Do not run analog and digi-

tal (especially clock) lines parallel to one another, or

digital lines underneath the ADC package.

Figure 18 shows the recommended system ground

connections. A single-point analog ground (“star”

ground point) should be established at AGND, sepa-

rate from the logic ground. All other analog grounds

and DGND should be connected to this ground. No

other digital system ground should be connected to

this single-point analog ground. The ground return to

the power supply for this ground should be low imped-

ance and as short as possible for noise-free operation.

High-frequency noise in the VDD power supply may

affect the high-speed comparator in the ADC. Bypass

these supplies to the single-point analog ground with

0.1µF and 4.7µF bypass capacitors close to the

MAX192. Minimize capacitor lead lengths for best sup-

ply-noise rejection. If the +5V power supply is very

noisy, a 10Ω resistor can be connected as a lowpass

filter, as shown in Figure 18.

High-Speed Digital Interfacing

The MAX192 can interface with QSPI at high through-

put rates using the circuit in Figure 19. This QSPI circuit

can be programmed to do a conversion on each of the

eight channels. The result is stored in memory without

taxing the CPU since QSPI incorporates its own

micro-sequencer.

Figure 20 details the code that sets up QSPI for

autonomous operation. In external clock mode, the

MAX192 performs a single-ended, unipolar conversion

on each of the eight analog input channels. Figure 21

shows the timing associated with the assembly code of

Figure 20. The first byte clocked into the MAX192 is the

control byte, which triggers the first conversion on CH0.

The last two bytes clocked into the MAX192 are all

zero, and clock out the results of the CH7 conversion.

______________________________________________________________________________________ 19

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