MAX192ACAP 데이터 시트보기 (PDF) - Maxim Integrated

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MAX192ACAP

Low-Power, 8-Channel,Serial 10-Bit ADC

Maxim Integrated 

Low-Power, 8-Channel,

Serial 10-Bit ADC

COMPLETE CONVERSION SEQUENCE

DIN 1

00

FULLPD

2.5V

REFADJ

0V

4V

VREF

0V

(ZEROS)

2ms WAIT

1

01

FASTPD

CH1

1

11

NOPD

τ = RC = 20kΩ x CREFADJ

tBUFFEN ≈ 15µs

Figure 13. FULLPD/FASTPD Power-Up Sequence

FULL POWER-DOWN

1000

10,000

CH7

1

00

FULLPD

(ZEROS)

1

01

FASTPD

FAST POWER-DOWN

8 CHANNELS

100

1 CHANNEL

8 CHANNELS

1000

1 CHANNEL

10

2ms FASTPD WAIT

400kHz EXTERNAL CLOCK

INTERNAL COMPENSATION

1

0

100 200 300 400 500

CONVERSIONS PER CHANNEL PER SECOND

Figure 14a. Supply Current vs. Sample Rate/Second, FULLPD,

400kHz Clock

RC filter with the internal 20kΩ reference resistor with a

0.2ms time constant. To achieve full 10-bit accuracy,

10 time constants or 2ms are required after power-up.

Waiting 2ms in FASTPD mode instead of full power-up

will reduce the power consumption by a factor of 10 or

more. This is achieved by using the sequence shown in

Figure 13.

Lowest Power at Higher Throughputs

Figure 14b shows the power consumption with

external-reference compensation in fast power-down,

with one and eight channels converted. The external

4.7µF compensation requires a 50µs wait after

power-up, accomplished by 75 idle clocks after a

dummy conversion. This circuit combines fast

multi-channel conversion with lowest power consump-

tion possible. Full power-down mode may provide

increased power savings in applications where the

100

2MHz EXTERNAL CLOCK

EXTERNAL COMPENSATION

50µs WAIT

10

0

4k

8k

12k

16k

CONVERSIONS PER CHANNEL PER SECOND

Figure 14b. Supply Current vs. Sample Rate/Second, FASTPD,

2MHz Clock

3.0

2.5

2.0

1.5

1.0

0.5

0

0.0001 0.001 0.01 0.1

1

10

TIME IN SHUTDOWN (sec)

Figure 14c. Typical Power-Up Delay vs. Time in Shutdown

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