MAX192ACAP 데이터 시트보기 (PDF) - Maxim Integrated

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MAX192ACAP

Low-Power, 8-Channel,Serial 10-Bit ADC

Maxim Integrated 

Low-Power, 8-Channel,

Serial 10-Bit ADC

CLOCK

MODE

SHDN

DIN

INTERNAL

SETS EXTERNAL

CLOCK MODE

SXXXXX11

EXTERNAL

SX X XXX0 1

SETS FAST

POWER-DOWN

MODE

SETS EXTERNAL

CLOCK MODE

S XX XXX1 1

EXTERNAL

DOUT

MODE

DATA VALID

(10 + 2 DATA BITS)

POWERED UP

DATA VALID

(10 + 2 DATA BITS)

VALID DATA INVALID

FAST POWERED UP

POWER-DOWN

FULL

POWER-

DOWN

POWERED

UP

Figure 12a. Timing Diagram Power-Down Modes, External Clock

CLOCK

MODE

SETS INTERNAL

CLOCK MODE

INTERNAL CLOCK MODE

SETS FULL

POWER-DOWN

DIN

SXXXXX10

SX X XXX0 0

S

DOUT

DATA VALID

DATA VALID

SSTRB

MODE

CONVERSION

POWERED UP

CONVERSION

FULL

POWER-DOWN

POWERED

UP

Figure 12b. Timing Diagram Power-Down Modes, Internal Clock

Power-Down

Choosing Power-Down Mode

You can save power by placing the converter in a

low-current shutdown state between conversions.

Select full power-down or fast power-down mode via

bits 1 and 0 of the DIN control byte with SHDN either

high or floating (see Tables 3 and 6). Pull SHDN low at

any time to shut down the converter completely. SHDN

overrides bits 1 and 0 of DIN word (see Table 7).

Full power-down mode turns off all chip functions that

draw quiescent current, typically reducing IDD to 2µA.

Fast power-down mode turns off all circuitry except the

bandgap reference. With the fast power-down mode, the

supply current is 30µA. Power-up time can be shortened

to 5µs in internal compensation mode.

In both software shutdown modes, the serial interface

remains operational, however, the ADC will not convert.

Table 5 illustrates how the choice of reference-buffer

compensation and power-down mode affects both

power-up delay and maximum sample rate.

In external compensation mode, the power-up time is

20ms with a 4.7µF compensation capacitor when the

capacitor is fully discharged. In fast power-down, you

can eliminate start-up time by using low-leakage capaci-

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