EBR25UC8ABFD 데이터 시트보기 (PDF) - Elpida Memory, Inc

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EBR25UC8ABFD

256MB Direct Rambus™ DRAM RIMM™ Module

Elpida Memory, Inc 

EBR25UC8ABFD

AC Electrical Specifications

Symbol

Parameter and Conditions

Grade min.

typ.

max.

Unit

Z

Module Impedance of RSL signals

25.2

28.0

30.8

Ω

Module Impedance of SCK and CMD signals

23.8

28.0

32.2

Ω

TPD

Average clock delay from finger to finger of all RSL

clock nets (CTM, CTMN,CFM, and CFMN)

—

—

1.56

ns

∆TPD

Propagation delay variation of RSL signals with respect

to TPD *1, 2

−21

—

21

ps

∆TPD-CMOS

Propagation delay variation of SCK signal with respect

to an average clock delay *1

−250

—

250

ps

∆TPD- SCK,CMD

Propagation delay variation of CMD signal with respect

to SCK signal

−200

—

200

ps

Vα/VIN

Attenuation Limit

-AEP

-AE

-AD

—

—

17.0

%

-8C

VXF/VIN

Forward crosstalk coefficient

(300ps input rise time 20% - 80%)

-AEP

-AE

-AD

—

—

4.0

%

-8C

VXB/VIN

Backward crosstalk coefficient

(300ps input rise time 20% - 80%)

-AEP

-AE

-AD

—

—

2.0

%

-8C

RDC

DC Resistance Limit

-AEP

-AE

-AD

—

—

0.8

Ω

-8C

Notes 1. TPD or Average clock delay is defined as the average delay from finger to finger of all RSL clock nets

(CTM, CTMN, CFM, and CFMN).

2. If the RIMM module meets the following specification, then it is compliant to the specification.

If the RIMM module does not meet these specifications, then the specification can be adjusted by the

“Adjusted ∆TPD Specification” table.

Adjusted ∆TPD Specification

Absolute

Symbol Parameter and conditions

Adjusted min./max.

min.

max.

Unit

∆TPD

Propagation delay variation of RSL signals with

respect to TPD

+/− [17+(18*N*∆Z0)] *1

−30

30

ps

Note: 1 N = Number of RDRAM devices installed on the RIMM module.

∆Z0 = delta Z0% = (max. Z0 - min. Z0) / (min. Z0)

(max. Z0 and min. Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL

layers on the module.)

Data Sheet E0317E20 (Ver. 2.0)

8

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