EBR25UC8ABFD 데이터 시트보기 (PDF) - Elpida Memory, Inc

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EBR25UC8ABFD

256MB Direct Rambus™ DRAM RIMM™ Module

Elpida Memory, Inc 

EBR25UC8ABFD

Module Connector Pad Description

Signal

GND

Module

Connector Pads

I/O

A1, A3, A5, A7, A9, A11,

A13, A15, A17, A19, A21,

A23, A25, A27, A29, A31,

A33, A39, A52, A60, A62,

A64, A66, A68, A70, A72,

A74, A76, A78, A80, A82,

A84, A86, A88, A90, A92,

B1, B3, B5, B7, B9, B11,

—

B13, B15, B17, B19, B21,

B23, B25, B27, B29, B31,

B33, B39, B52, B60, B62,

B64, B66, B68, B70, B72,

B74, B76, B78, B80, B82,

B84, B86, B88, B90, B92

LCFM

B10

I

LCFMN

B12

I

LCMD

B34

I

LCOL4..LCOL0 A20, B20, A22, B22, A24 I

LCTM

A14

I

LCTMN

A12

I

LDQA8..LDQA0

LDQB8..LDQB0

A2,

B8,

B2,A4,

A10

B4,

A6,

B6,

A8,

I/O

B32, A32, B30, A30, B28,

A28, B26, A26, B24

I/O

LROW2..LROW0 B16, A18, B18

I

LSCK

NC

RCFM

A34

I

A16, B14, A38, B38, A40,

B40, A77, B79, A43, B43,

A44, B44, A45, B45, A46, —

B46, A47, B47, A48, B48,

A49, B49, A50, B50

B83

I

RCFMN

B81

I

RCMD

B59

I

RCOL4..RCOL0 A73, B73, A71, B71, A69 I

RCTM

A79

I

RCTMN

A81

I

RDQA8..RDQA0

RDQB8..RDQB0

A91, B91, A89, B89, A87,

B87, A85, B85, A83

I/O

B61, A61, B63, A63, B65,

A65, B67, A67, B69

I/O

RROW2..RROW0 B77, A75, B75

I

Type

Description

—

Ground reference for RDRAM core and interface. 72

PCB connector pads.

RSL

RSL

VCMOS

RSL

RSL

RSL

RSL

RSL

RSL

VCMOS

—

RSL

RSL

VCMOS

RSL

RSL

RSL

RSL

RSL

RSL

Clock from master. Interface clock used for receiving

RSL signals from the Channel. Positive polarity.

Clock from master. Interface clock used for receiving

RSL signals from the Channel. Negative polarity.

Serial Command used to read from and write to the

control registers. Also used for power management.

Column bus. 5-bit bus containing control and address

information for column accesses.

Clock to master. Interface clock used for transmitting

RSL signals to the Channel. Positive polarity.

Clock to master. Interface clock used for transmitting

RSL signals to the Channel. Negative polarity.

Data bus A. A 9-bit bus carrying a byte of read or write

data between the Channel and the RDRAM.

Data bus B. A 9-bit bus carrying a byte of read or write

data between the Channel and the RDRAM.

Row bus. 3-bit bus containing control and address

information for row accesses.

Serial clock input. Clock source used to read from and

write to the RDRAM control registers.

These pads are not connected. These 24 connector

pads are reserved for future use.

Clock from master. Interface clock used for receiving

RSL signals from the Channel. Positive polarity.

Clock from master. Interface clock used for receiving

RSL signals from the Channel. Negative polarity.

Serial Command Input used to read from and write to

the control registers. Also used for power

management.

Column bus. 5-bit bus containing control and address

information for column accesses.

Clock to master. Interface clock used for transmitting

RSL signals to the Channel. Positive polarity.

Clock to master. Interface clock used for transmitting

RSL signals to the Channel. Negative polarity.

Data bus A. A 9-bit bus carrying a byte of read or write

data between the Channel and the RDRAM.

Data bus B. A 9-bit bus carrying a byte of read or write

data between the Channel and the RDRAM.

Row bus. 3-bit bus containing control and address

information for row accesses.

Data Sheet E0317E20 (Ver. 2.0)

4

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