MT89L80 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT89L80

CMOS ST-BUS™ FAMILY Digital Switch

Zarlink Semiconductor Inc 

MT89L80

Mode

Control

Bits

(unused)

Memory

Select

Bits

Stream

Address

Bits

Data Sheet

7

6

5

4

3

2

1

0

Bit

Name

Description

6

Message When 1, the contents of the Connection Memory Low are output on the Serial Output

Mode streams except when the ODE pin is low. When 0, the Connection Memory bits for each

channel determine what is output.

5

(unused)

4-3 Memory 0-0 - Not to be used

Select Bits 0-1 - Data Memory (read only from the microprocessor port)

1-0 - Connection Memory Low

1-1 - Connection Memory High

2-0

Stream The number expressed in binary notation on these bits refers to the input or output ST-BUS

Address Bits stream which corresponds to the subsection of memory made accessible for subsequent

operations.

Figure 4 - Control Register Bits

No Corresponding Memory

- These bits give 0s if read.

Per Channel

Control Bits

7

6

5

4

3

2

1

0

Bit

Name

Description

2

Message When 1, the contents of the corresponding location in Connection Memory Low are

Channel output on the location’s channel and stream. When 0, the contents of the corresponding

location in Connection Memory Low act as an address for the Data Memory and so

determine the source of the connection to the location’s channel and stream.

1

CSTo Bit This bit is output on the CSTo pin one channel early. The CSTo bit for stream 0 is output

first.

0

Output If the ODE pin is high and bit 6 of the Control Register is 0, then this bit enables the

Enable output driver for the location’s channel and stream. This allows individual channels on

individual streams to be made high-impedance, allowing switching matrices to be

constructed. A 1 enables the driver and a 0 disables it.

Figure 5 - Connection Memory High Bits

6

Zarlink Semiconductor Inc.

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