MT89L80 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc
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MT89L80 Datasheet PDF : 17 Pages
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MT89L80
Data Sheet
A5 A4 A3 A2 A1 A0 Hex Address
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
00 - 1F
20
21
•
•
•
3F
* Writing to the Control Register is the only fast transaction.
† Memory and stream are specified by the contents of the Control Register.
Figure 3 - Address Memory Map
Location
Control Register *
Channel 0†
Channel 1†
•
•
•
Channel 31†
Software Control
The address lines on the Control Interface give access to the Control Register directly or, depending on the
contents of the Control Register, to the High or Low sections of the Connection Memory or to the Data Memory.
If address line A5 is low, then the Control Register is addressed regardless of the other address lines (see Fig. 3). If
A5 is high, then the address lines A4-A0 select the memory location corresponding to channel 0-31 for the memory
and stream selected in the Control Register.
The data in the Control Register consists of mode control bits, memory select bits, and stream address bits (see
Fig. 4). The memory select bits allow the Connection Memory High or Low or the Data Memory to be chosen, and
the stream address bits define one of the ST-BUS input or output streams.
Bit 7 of the Control Register allows split memory operation - reads are from the Data Memory and writes are to the
Connection Memory Low.
The other mode control bit, bit 6, puts every output channel on every output stream into active Message Mode; i.e.,
the contents of the Connection Memory Low are output on the ST-BUS output streams once every frame unless the
ODE pin is low. In this mode the chip behaves as if bits 2 and 0 of every Connection Memory High location were 1,
regardless of the actual values.
Mode
Control
Bits
(unused)
Memory
Select
Bits
Stream
Address
Bits
7
6
5
4
3
2
1
0
Bit
Name
Description
7 Split Memory When 1, all subsequent reads are from the Data Memory and writes are to the Connection
Memory Low, except when the Control Register is accessed again. When 0, the Memory
Select bits specify the memory for subsequent operations. In either case, the Stream
Address Bits select the subsection of the memory which is made available.
5
Zarlink Semiconductor Inc.
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