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MT89L80

CMOS ST-BUS™ FAMILY Digital Switch

Zarlink Semiconductor Inc 

MT89L80

Data Sheet

The serial streams of the ST-BUS operate continuously at 2048 kbit/s and are arranged in 125 µs wide frames

which contain 32 8-bit channels. Zarlink manufactures a number of devices which interface to the ST-BUS; a key

device being the MT89L80 chip.

The MT89L80 can switch data from channels on ST-BUS inputs to channels on ST-BUS outputs, and

simultaneously allows its controlling microprocessor to read channels on ST-BUS inputs or write to channels on ST-

BUS outputs (Message Mode). To the microprocessor, the MT89L80 looks like a memory peripheral. The

microprocessor can write to the MT89L80 to establish switched connections between input ST-BUS channels and

output ST-BUS channels, or to transmit messages on output ST-BUS channels. By reading from the MT89L80, the

microprocessor can receive messages from ST-BUS input channels or check which switched connections have

already been established.

By integrating both switching and interprocessor communications, the MT89L80 allows systems to use distributed

processing and to switch voice or data in an ST-BUS architecture.

Hardware Description

Serial data at 2048 kbit/s is received at the eight ST-BUS inputs (STi0 to STi7), and serial data is transmitted at the

eight ST-BUS outputs (STo0 to STo7). Each serial input accepts 32 channels of digital data, each channel

containing an 8-bit word which may represent a PCM-encoded analog/voice sample as provided by a codec (e.g.,

Zarlink’s MT8964).

This serial input word is converted into parallel data and stored in the 256 X 8 Data Memory. Locations in the Data

Memory are associated with particular channels on particular ST-BUS input streams. These locations can be read

by the microprocessor which controls the chip.

Locations in the Connection Memory, which is split into high and low parts, are associated with particular ST-BUS

output streams. When a channel is due to be transmitted on an ST-BUS output, the data for the channel can either

be switched from an ST-BUS input or it can originate from the microprocessor. If the data is switched from an input,

then the contents of the Connection Memory Low location associated with the output channel is used to address

the Data Memory. This Data Memory address corresponds to the channel on the input ST-BUS stream on which the

data for switching arrived. If the data for the output channel originates from the microprocessor (Message Mode),

then the contents of the Connection Memory Low location associated with the output channel are output directly,

and this data is output repetitively on the channel once every frame until the microprocessor intervenes.

The Connection Memory data is received, via the Control Interface, at D7 to D0. The Control Interface also receives

address information at A5 to A0 and handles the microprocessor control signals CS, DTA, R/W and DS. There are

two parts to any address in the Data Memory or Connection Memory. The higher order bits come from the Control

Register, which may be written to or read from via the Control Interface. The lower order bits come from the address

lines directly.

The Control Register also allows the chip to broadcast messages on all ST-BUS outputs (i.e., to put every channel

into Message Mode), or to split the memory so that reads are from the Data Memory and writes are to the

Connection Memory Low. The Connection Memory High determines whether individual output channels are in

Message Mode, and allows individual output channels to go into a high-impedance state, which enables arrays of

MT89L80s to be constructed. It also controls the CSTo pin.

All ST-BUS timing is derived from the two signals C4i and F0i.

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Zarlink Semiconductor Inc.

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