MT89L80 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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MT89L80

CMOS ST-BUS™ FAMILY Digital Switch

Zarlink Semiconductor Inc 

MT89L80

Data Sheet

Pin Description (continued)

Pin #

44 48

PLCC SSOP

Name

Description

14 15

15-17 16-18

C4i

A0-2

4.096 MHz Clock (5 V-tolerant Input). ST-BUS bit cell boundaries lie on the alternate

falling edges of this clock.

Address 0-2 / Input Streams 8-10 (5 V-tolerant Input). These are the inputs for the

address lines on the microprocessor interface.

19-21 20-22 A3-5 Address 3-5 / Input Streams 11-13 (5 V-tolerant Input). These are the inputs for the

address lines on the microprocessor interface.

22

23

DS Data Strobe (5 V-tolerant Input). This is the input for the active high data strobe on the

microprocessor interface.

23 24

24 26

25-27 27-29

29-33 31-35

R/W Read/Write (5 V-tolerant Input). This is the input for the read/write signal on the

microprocessor interface - high for read, low for write.

CS Chip Select (5 V-tolerant Input). This is the input for the active low chip select on the

microprocessor interface

D7-D5 Data Bus (5 V-tolerant I/O): These are the bidirectional data pins on the

microprocessor interface.

D4-D0 Data Bus (5 V-tolerant I/O): These are the bidirectional data pins on the

microprocessor interface.

34

1,

VSS Ground.

25,37

35-39 38-42 STo7-3 ST-BUS Outputs 7 to 3 (5 V-Tolerant Three-state Outputs). These are the pins for the

eight 2048 kbit/s ST-BUS output streams.

41-43 44-46 STo2-0 ST-BUS Outputs 2to 0 (5 V-Tolerant Three-state Outputs). These are the pins for the

eight 2048kbit/s ST-BUS output streams.

44 47 ODE Output Drive Enable (5 V-tolerant Input). If this input is held high, the STo0-STo7

output drivers function normally. If this input is low, the STo0-STo7 output drivers go into

their high impedance state. NB: Even when ODE is high, channels on the STo0-STo7

outputs can go high impedance under software control.

1

48

6, 18, 6, 19,

28, 40 30, 43

CSTo

NC

Control ST-BUS Output (5 V-Tolerant Output). Each frame of 256 bits on this ST-BUS

output contains the values of bit 1 in the 256 locations of the Connection Memory High.

No Connection.

Functional Description

In recent years, there has been a trend in telephony towards digital switching, particularly in association with

software control. Simultaneously, there has been a trend in system architectures towards distributed processing or

multi-processor systems.

In accordance with these trends, Zarlink has devised the ST-BUS (Serial Telecom Bus). This bus architecture can

be used both in software-controlled digital voice and data switching, and for interprocessor communications. The

uses in switching and in interprocessor communications are completely integrated to allow for a simple general

purpose architecture appropriate for the systems of the future.

3

Zarlink Semiconductor Inc.

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