CY7C146-45JI 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C146-45JI

2K x 8 Dual-Port Static RAM

Cypress Semiconductor 

CY7C132, CY7C136

CY7C136A, CY7C142, CY7C146

Switching Waveforms (continued)

Figure 8. Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)[12, 21]

ADDRESS

CE

R/W

DATAIN

DOUT

tWC

tSCE

tHA

tAW

tSA

tPWE

tHZWE

tSD

tHD

DATA VALID

tLZWE

HIGH IMPEDANCE

CEL Valid First:

ADDRESSL,R

CEL

CER

BUSYR

CER Valid First:

ADDRESSL,R

CER

CEL

BUSYL

Figure 9. Busy Timing Diagram No. 1 (CE Arbitration)

ADDRESS MATCH

tPS

tBLC

tBHC

ADDRESS MATCH

tPS

tBLC

tBHC

Note

21. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high impedance state.

Document #: 38-06031 Rev. *E

Page 9 of 15

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