CY7C146-45JI 데이터 시트보기 (PDF) - Cypress Semiconductor
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CY7C146-45JI Datasheet PDF : 15 Pages
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CY7C132, CY7C136
CY7C136A, CY7C142, CY7C146
Switching Characteristics
Over the Operating Range (Speeds -15, -25, -30) [8] (continued)
Parameter
Description
Write Cycle[12]
tWC
Write Cycle Time
tSCE
CE LOW to Write End
tAW
Address Setup to Write End
tHA
Address Hold from Write End
tSA
Address Setup to Write Start
tPWE
R/W Pulse Width
tSD
Data Setup to Write End
tHD
tHZWE
tLZWE
Data Hold from Write End
R/W LOW to High Z [7]
R/W HIGH to Low Z [7]
Busy/Interrupt Timing
tBLA
tBHA
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch[13]
tBLC
tBHC
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH[13]
tPS
Port Set Up for Priority
tWB
R/W LOW after BUSY LOW[14]
tWH
R/W HIGH after BUSY HIGH
tBDD
BUSY HIGH to Valid Data
tDDD
Write Data Valid to Read Data Valid
tWDD
Write Pulse to Data Delay
Interrupt Timing [16]
tWINS
tEINS
tINS
tOINR
tEINR
tINR
R/W to INTERRUPT Set Time
CE to INTERRUPT Set Time
Address to INTERRUPT Set Time
OE to INTERRUPT Reset Time[13]
CE to INTERRUPT Reset Time[13]
Address to INTERRUPT Reset Time[13]
Shaded areas contain preliminary information.
7C136-15 [4]
7C146-15
Min
Max
15
12
12
2
0
12
10
0
10
0
15
15
15
15
5
0
13
15
Note 15
Note 15
15
15
15
15
15
15
7C132-25 [4]
7C136-25
7C142-25
7C146-25
Min
Max
25
20
20
2
0
15
15
0
15
0
20
20
20
20
5
0
20
25
Note 15
Note 15
25
25
25
25
25
25
7C132-30
7C136-30
7C142-30
7C146-30
Min
Max
30
25
25
2
0
25
15
0
15
0
20
20
20
20
5
0
30
30
Note 15
Note 15
25
25
25
25
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
12. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write.
13. These parameters are measured from the input signal changing, until the output pin goes to a high impedance state.
14. CY7C142/CY7C146 only.
15. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B’s address toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
16. 52-pin PLCC and PQFP versions only.
Document #: 38-06031 Rev. *E
Page 5 of 15
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