CY7C146-45JI 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C146-45JI

2K x 8 Dual-Port Static RAM

Cypress Semiconductor 

CY7C132, CY7C136

CY7C136A, CY7C142, CY7C146

Switching Waveforms (continued)

Figure 6. Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7C136/CY7C136A)

ADDRESSR

R/WR

tRC

ADDRESS MATCH

tPWE

DINR

ADDRESSL

BUSYL

DOUTL

tPS

tBLA

VALID

ADDRESS MATCH

tBHA

tWDD

tDDD

tBDD

VALID

ADDRESS

CE

R/W

DATAIN

OE

DOUT

Figure 7. Write Cycle No.1 (OE Three-States Data I/Os—Either Port) [12, 20]

tWC

tSCE

tAW

tHA

tSA

tPWE

tSD

tHD

DATA VALID

tHZOE

HIGH IMPEDANCE

Note

20. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance

and for data to be placed on the bus for the required tSD.

Document #: 38-06031 Rev. *E

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