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IDT7026L35G 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT7026L35G
IDT
Integrated Device Technology IDT
IDT7026L35G Datasheet PDF : 18 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
IDT7026S/L
High-Speed 16K x 16 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(5,6)
Symbol
Parameter
7026X15
Com'l Only
7026X20
Com'l, Ind
& Military
7026X25
Com'l, Ind
& Military
Min. Max. Min. Max. Min. Max. Unit
WRITE CYCLE
tWC
Write Cycle Time
tEW
Chip Enable to End-of-Write(3)
15
____
20
____
25
____
ns
12
____
15
____
20
____
ns
tAW
Address Valid to End-of-Write
tAS
Address Set-up Time(3)
12
____
15
____
20
____
ns
0
____
0
____
0
____
ns
tWP
Write Pulse Width
12
____
15
____
20
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
ns
tDW
Data Valid to End-of-Write
tHZ
Output High-Z Time(1,2)
tDH
Data Hold Time(4)
tWZ
Write Enable to Output in High-Z(1,2)
tOW
Output Active from End-of-Write(1,2,4)
10
____
15
____
15
____
ns
____
10
____
12
____
15
ns
0
____
0
____
0
____
ns
____
10
____
12
____
15
ns
0
____
0
____
0
____
ns
tSWRD
SEM Flag Write to Read Time
5
____
5
____
5
____
ns
tSPS
SEM Flag Contention Window
5
____
5
____
5
____
ns
Symbol
Parameter
7026X35
Com'l, Ind
& Military
Min. Max.
3199 tbl 13a
7026X55
Com'l, Ind
& Military
Min. Max. Unit
WRITE CYCLE
tWC
Write Cycle Time
tEW
Chip Enable to End-of-Write(3)
35
____
55
____
ns
30
____
45
____
ns
tAW
Address Valid to End-of-Write
tAS
Address Set-up Time(3)
30
____
45
____
ns
0
____
0
____
ns
tWP
Write Pulse Width
25
____
40
____
ns
tWR
Write Recovery Time
0
____
0
____
ns
tDW
Data Valid to End-of-Write
tHZ
Output High-Z Time(1,2)
tDH
Data Hold Time(4)
tWZ
Write Enable to Output in High-Z(1,2)
tOW
Output Active from End-of-Write(1,2,4)
15
____
30
____
ns
____
15
____
25
ns
0
____
0
____
ns
____
15
____
25
ns
0
____
0
____
ns
tSWRD
SEM Flag Write to Read Time
5
____
5
____
ns
tSPS
SEM Flag Contention Window
5
____
5
____
ns
NOTES:
2939 tbl 13b
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part numbers indicates power rating (S or L).
6.942

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