IDT7026L35G 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT7026L35G

HIGH-SPEED 16K X 16 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT7026S/L

High-Speed 16K x 16 Dual-Port Static RAM

WAVEFORM OF READ CYCLES(5)

tRC

ADDR

tAA (4)

CE

tACE (4)

tAOE (4)

OE

UB, LB

tABE (4)

Military, Industrial and Commercial Temperature Ranges

R/W

DATAOUT

tLZ (1)

tOH

VALID DATA (4)

tHZ (2)

BUSYOUT

tBDD (3, 4)

2939 drw 06

NOTES:

1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.

2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB.

3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

Timing of Power-Up Power-Down

CE

tPU

ICC

50%

ISB

tPD

50%

2939 drw 07 ,

6.842

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