83940BYT 데이터 시트보기 (PDF) - Integrated Device Technology
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83940BYT Datasheet PDF : 13 Pages
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Low Skew, 1-to-18 LVPECL-to-
LVCMOS/LVTTL Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015
ICS83940
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP
and VCMR input requirements. Figures 2A to 2E show interface
examples for the PCLK/nPCLK input driven by the most
common driver types. The input interfaces suggested here
are examples only. If the driver is from another vendor, use
their termination recommendation. Please consult with the
vendor of the driver component to confirm the driver
termination requirements.
3.3V
CML
Zo = 50 Ohm
Zo = 50 Ohm
3.3V
R1
R2
50
50
3.3V
PCLK
nPCLK HiPerClockS
PCLK/nPCLK
2.5V
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
2.5V
R3
R4
120
120
3.3V
PCLK
R1
R2
120
120
nPCLK
HiPerClockS
PCLK/nPCLK
FIGURE 2A. PCLK/NPCLK INPUT DRIVEN
BY A CML DRIVER
FIGURE 2B. PCLK/NPCLK INPUT DRIVEN
BY AN SSTL DRIVER
3. 3V
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
3. 3V
R3
R4
125
125
3.3V
PCLK
nPCLK HiPerClockS
I nput
R1
R2
84
84
3.3V
LVDS
Zo = 50 Ohm
R5
100
Zo = 50 Ohm
3.3V
3.3V
R3
R4
1K
1K
C1
PCLK
C2
nPCLK
HiPerClockS
PCLK/nPCLK
R1
R2
1K
1K
FIGURE 2C. PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 2D. PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
3.3V
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
3.3V
R3
R4
84
84
C1
C2
R5
100 - 200
R6
100 - 200
R1
R2
125
125
3.3V
PCLK
nPCLK HiPerClockS
PCLK/nPCLK
FIGURE 2E. PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
83940BY
www.idt.com
8
REV. B JANUARY 31, 2014
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