83940BYT 데이터 시트보기 (PDF) - Integrated Device Technology
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83940BYT Datasheet PDF : 13 Pages
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Low Skew, 1-to-18 LVPECL-to-
LVCMOS/LVTTL Fanout Buffer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015
ICS83940
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2, 12, 17, 25
GND
Power
Power supply ground.
3
LVCMOS_CLK
Input Pulldown Clock input. LVCMOS / LVTTL interface levels.
Clock select input. Selects LVCMOS / LVTTL clock
4
CLK_SEL
Input Pulldown input when HIGH. Selects PCLK, nPCLK inputs
when LOW. LVCMOS / LVTTL interface levels.
5
PCLK
Input Pulldown Non-inverting differential LVPECL clock input.
6
nPCLK
Input Pullup Inverting differential LVPECL clock input.
7, 21
8, 16, 29
9, 10, 11, 13, 14,
15, 18, 19, 20, 22,
23, 24, 26, 27, 28,
30, 31, 32
V
DD
VDDO
Q17, Q16, Q15, Q14, Q13,
Q12, Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4, Q3,
Q2, Q1, Q0
Power
Power
Output
Core supply pins.
Output supply pins.
Clock outputs. 16Ω typical output impedance.
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
CIN
Input Capacitance
CPD
Power Dissipation Capacitance
(per output)
RPULLUP
RPULLDOWN
ROUT
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
Test Conditions
VDD, VDDO = 3.47
VDD, VDDO = 2.625
Minimum
11
Typical
4
13
11
51
51
16
Maximum
21
Units
pF
pF
pF
KΩ
KΩ
Ω
TABLE 3A. CLOCK SELECT FUNCTION TABLE
Control Input
CLK_SEL
0
1
PCLK, nPCLK
Selected
De-selected
Clock
LVCMOS_CLK
De-selected
Selected
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
CLK_SEL LVCMOS_CLK
PCLK
nPCLK
Outputs
Q0:Q17
Input to Output Mode
Polarity
0
—
0
1
LOW
Differential to Single Ended Non Inverting
0
—
1
0
HIGH
Differential to Single Ended Non Inverting
0
—
0
—
0
Biased;
NOTE 1
LOW
Single Ended to Single Ended Non Inverting
1
Biased;
NOTE 1
HIGH
Single Ended to Single Ended Non Inverting
0
—
Biased; NOTE 1
0
HIGH
Single Ended to Single Ended Inverting
0
—
Biased; NOTE 1
1
LOW
Single Ended to Single Ended Inverting
1
0
—
—
LOW
Single Ended to Single Ended Non Inverting
1
1
—
—
HIGH
Single Ended to Single Ended Non Inverting
NOTE 1: Please refer to the Application Information section. "Wiring the Differential Input to Accept Single Ended Levels".
83940BY
www.idt.com
2
REV. B JANUARY 31, 2014
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