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83940BYT

Low Skew, 1-to-18 LVPECL-to-LVCMOS/LVTTL Fanout Buffer

Integrated Device Technology 

Low Skew, 1-to-18 LVPECL-to-

LVCMOS/LVTTL Fanout Buffer

PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015

APPLICATION INFORMATION

ICS83940

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

Figure 1 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = VDD/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V

and R2/R1 = 0.609.

VDD

Single Ended Clock Input

V_REF

C1

0.1u

R1

1K

PCLK

nPCLK

R2

1K

FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

83940BY

www.idt.com

7

REV. B JANUARY 31, 2014

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