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83940BYT

Low Skew, 1-to-18 LVPECL-to-LVCMOS/LVTTL Fanout Buffer

Integrated Device Technology 

Low Skew, 1-to-18 LVPECL-to-

LVCMOS/LVTTL Fanout Buffer

PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015

ICS83940

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, VDD

Inputs, VI

Outputs, VO

Package Thermal Impedance, θJA

Storage Temperature, TSTG

4.6V

-0.5V to VDD + 0.5 V

-0.5V to VDDO + 0.5V

47.9°C/W (0 lfpm)

-65°C to 150°C

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device.These ratings are stress specifications only. Functional

operation of product at these conditions or any conditions be-

yond those listed in the DC Characteristics or AC Character-

istics is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect product reliability.

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0° TO 70°

Symbol Parameter

VDD

VDDO

IDD

IDDO

Core Supply Voltage

Output Supply Voltage

Power Supply Current

Output Supply Current

Test Conditions

Minimum

3.135

3.135

Typical

3.3

3.3

Maximum

3.465

3.465

25

25

Units

V

V

mA

mA

TABLE

4B. DC

CHARACTERISTICS,

V

DD

=V =

DDO

3.3V±5%, TA = 0° TO

70°

Symbol Parameter

Test Conditions

Minimum Typical

VIH

VIL

VPP

VCMR

Input High Voltage LVCMOS_CLK

Input Low Voltage LVCMOS_CLK

Peak-to-Peak

Input Voltage

Input Common Mode

Voltage; NOTE 1, 2

PCLK, nPCLK

PCLK, nPCLK

2.4

300

GND + 1.5

I

Input Current

IN

VOH

Output High Voltage

IOH = -20mA

2.4

V

Output Low Voltage

OL

I = 20mA

OL

NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is V + 0.3V.

DD

NOTE 2: Common mode voltage is defined as VIH.

Maximum

VDD

0.8

VDD

±200

0.5

Units

V

V

mV

V

µA

V

V

83940BY

www.idt.com

3

REV. B JANUARY 31, 2014

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