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PCA9540B

2-channel I2C multiplexer

Philips Electronics 

Philips Semiconductors

2-channel I2C multiplexer

Product data sheet

PCA9540B

DEVICE ADDRESSING

Following a START condition the bus master must output the

address of the slave it is accessing. The address of the PCA9540B

is shown in Figure 3.

1 1 1 0 0 0 0 R/W

FIXED

SW00713

Figure 3. Slave address

The last bit of the slave address defines the operation to be

performed. When set to logic 1, a read is selected while a logic 0

selects a write operation.

CONTROL REGISTER

Following the successful acknowledgement of the slave address,

the bus master will send a byte to the PCA9540B which will be

stored in the Control Register. If multiple bytes are received by the

PCA9540B, it will save the last byte received. This register can be

written and read via the I2C bus.

CHANNEL SELECTION BITS

(READ/WRITE)

7 6 5 43 2 1 0

X X X X X B2 B1 B0

ENABLE BIT

Figure 4. Control register

SW00839

CONTROL REGISTER DEFINITION

A SCx/SDx downstream pair, or channel, is selected by the contents

of the control register. This register is written after the PCA9540B

has been addressed. The 2 LSBs of the control byte are used to

determine which channel is to be selected. When a channel is

selected, the channel will become active after a stop condition has

been placed on the I2C bus. This ensures that all SCx/SDx lines will

be in a HIGH state when the channel is made active, so that no

false conditions are generated at the time of connection.

Table 1. Control Register; Write — Channel Selection/

Read — Channel Status

D7 D6 D5 D4 D3 B2 B1 B0

COMMAND

X X X X X 0 X X No channel selected

X X X X X 1 0 0 Channel 0 enabled

X X X X X 1 0 1 Channel 1 enabled

X X X X X 1 1 X No channel selected

0 0 0 0 0 0 0 0 No channel selected;

power-up default state

POWER-ON RESET

When power is applied to VDD, an internal Power-On Reset holds

the PCA9540B in a reset condition until VDD has reached VPOR. At

this point, the reset condition is released and the PCA9540B

registers and I2C state machine are initialized to their default states,

all zeroes causing all the channels to be deselected. Thereafter,

VDD must be lowered below 0.2 V to reset the device.

VOLTAGE TRANSLATION

The pass gate transistors of the PCA9540B are constructed such

that the VDD voltage can be used to limit the maximum voltage that

will be passed from one I2C bus to another.

5.0

4.5

4.0

3.5

Vpass

3.0

2.5

2.0

1.5

1.0

2.0

Vpass vs. VDD

MAXIMUM

TYPICAL

2.5

3.0

3.5

4.0

VDD

MINIMUM

4.5

5.0

5.5

SW00820

Figure 5. Vpass voltage

Figure 5 shows the voltage characteristics of the pass gate

transistors (note that the graph was generated using the data

specified in the DC Characteristics section of this datasheet). In

order for the PCA9540B to act as a voltage translator, the Vpass

voltage should be equal to, or lower than the lowest bus voltage. For

example, if the main bus was running at 5 V, and the downstream

buses were 3.3 V and 2.7 V, then Vpass should be equal to or below

2.7 V to effectively clamp the downstream bus voltages. Looking at

Figure 5, we see that Vpass (max.) will be at 2.7 V when the

PCA9540B supply voltage is 3.5 V or lower so the PCA9540B

supply voltage could be set to 3.3 V. Pull-up resistors can then be

used to bring the bus voltages to their appropriate levels (see Figure

12).

More Information can be found in Application Note AN262 PCA954X

family of I2C/SMBus multiplexers and switches.

2004 Sep 29

4

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