E5551 데이터 시트보기 (PDF) - Temic Semiconductors

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E5551

Standard R/W Identification IC with Anticollision

Temic Semiconductors 

e5551

01

11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

reserved

lock bit (never transmitted)

BR

MS1 MS2 PSKCF

[2] [1] [0] * [1] [0] [2] [1] [0] [1] [0]

”0”

MAXBLK

* [2] [1] [0]

”0”

res’d

*useSTOP

AOR

useBT

useST

usePWD

Key:

–––––––––––––––––––––––––––––––––––––

AOR

Anwer-On-Request

BT

use Block Terminator

ST

use Sequence Terminator

PWD

use Password

STOP

obey stop header (active low!)

BR

Bit Rate

MS1

Modulator Stage 1

MS2

Modulator Stage 2

PSKCF PSK Clock Frequency

MAXBLK see Maxblock feature

reserved do not use

* Bit 15 and 24 must always be at ”0”,

otherwise malfunction will appear.

send blocks:

0000

0011

0 1 0 1 to 2

0 1 1 1 to 3

1 0 0 1 to 4

1 0 1 1 to 5

1 1 0 1 to 6

1 1 1 1 to 7

0 0 RF/2

0 1 RF/4

1 0 RF/8

1 1 reserved

0 0 0 direct

0 0 1 psk1 (phase change when input changes)

0 1 0 psk2 (phase change on bitclk if input high)

0 1 1 psk3 (phase change on rising edge of input)

–––––––––––––––––––––––––––––––––––

o/p freq. DATA=1

DATA=0

1 0 0 fsk1

rf/8

rf/5

1 0 1 fsk2

rf/8

rf/10

1 1 0 fsk1a

rf/5

rf/8

1 1 1 fsk2a

rf/10

rf/8

0 0 direct

0 1 Manchester

1 0 Biphase

1 1 reserved

0 0 0 RF/8

0 0 1 RF/16

0 1 0 RF/32

0 1 1 RF/40

1 0 0 RF/50

1 0 1 RF/64

1 1 0 RF/100

1 1 1 RF/128

bitrate_8cpb

bitrate_16cpb

bitrate_32cpb

bitrate_40cpb

bitrate_50cpb

bitrate_64cpb

bitrate_100cpb

bitrate_128cpb

Figure 7. Memory map of block 0

Rev. A2, 19-Apr-00

5 (21)

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