E5551 데이터 시트보기 (PDF) - Temic Semiconductors

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E5551

Standard R/W Identification IC with Anticollision

Temic Semiconductors 

e5551

Coil 1

Coil 2

Modulator

Mode register

Controller

Test logic

POR

Memory

(264 bit EEPROM)

Input register

HV generator

VDD VSS

Test pads

Figure 4. Block diagram e5551

Power-On Reset (POR)

The power-on reset is a delay reset which is triggered

when supply voltage is applied.

Mode Register

The mode register stores the mode data from EEPROM

block 0. It is continually refreshed at the start of every

block. This increases the reliability of the device (if the

originally loaded mode information is false, it will be

corrected by subsequent refresh cycles).

Modulator

The modulator consists of several data encoders in two

stages, which may be freely combined to obtain the

desired modulation. The basic types of modulation are:

D PSK: phase shift: 1) every change; 2) every ‘1’;

3) every rising edge (carrier: fc/2, fc/4 or fc/8)

D FSK: 1) f1 = rf/8 f2 = rf/5; 2) f1 = rf/8, f2 = rf/10

D Manchester: rising edge = H; falling edge = L

D Biphase: every bit creates a change, a data ‘H’ creates

an additional mid-bit change

Note: The following modulation type combinations will

not work:

D Stage1 Manchester or Biphase, stage2 PSK2, at any

PSK carrier frequency (because the first stage output

frequency is higher than the second stage strobe

frequency)

D Stage1 Manchester or Biphase and stage2 PSK with

bitrate = rf/8 and PSK carrier frequency = rf/8 (for the

same reason as above)

D Any stage1 option with any PSK for bitrates rf/50 or

rf/100 if the PSK carrier frequency is not an integer

multiple of the bitrate (e.g., br = rf/50, PSKcf = rf/4,

because 50/4 = 12.5). This is because the PSK carrier

frequency must maintain constant phase with respect

to the bit clock.

Rev. A2, 19-Apr-00

3 (21)

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