A3G4250D 데이터 시트보기 (PDF) - STMicroelectronics
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A3G4250D Datasheet PDF : 44 Pages
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A3G4250D
Mechanical and electrical characteristics
2.4.2
I2C - inter IC control interface
Subject to general operating conditions for Vdd and Top.
Table 8. I2C slave timing values
Symbol
Parameter
I2C standard mode(1)
Min.
Max.
f(SCL)
SCL clock frequency
0
100
tw(SCLL)
SCL clock low time
4.7
tw(SCLH) SCL clock high time
4.0
tsu(SDA)
th(SDA)
SDA setup time
SDA data hold time
250
0
3.45
th(ST)
START condition hold time
4
tsu(SR)
Repeated START condition
setup time
4.7
tsu(SP)
STOP condition setup time
4
tw(SP:SR)
Bus free time between STOP
and START condition
4.7
1. Data based on standard I2C protocol requirement; not tested in production.
Figure 5. I2C slave timing diagram(f)
67$57
6'$
I2C fast mode(1)
Min.
Max.
Unit
0
400
kHz
1.3
µs
0.6
100
ns
0
0.9
µs
0.6
0.6
µs
0.6
1.3
5(3($7('
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WVX 65
WZ 63 65
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WI 6'$
6&/
WU 6'$
WVX 6'$
WK 6'$
WVX 63
6723
WK 67 WZ 6&//
WZ 6&/+
WU 6&/
WI 6&/
!-V
f. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
Doc 022768 Rev 3
13/44
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