NJU6635CH 데이터 시트보기 (PDF) - Japan Radio Corporation

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NJU6635CH

16-CHARACTER 2-LINE DOT MATRIX LCD CONTROLLER DRIVER

Japan Radio Corporation  

NJU6635

l) Read Data from CG or DD RAM

• Read data to DD RAM

RS R/W DB7 DB6 DB5 DB4

Code 1 1 D D D D

← Higher order bit →

DB3 DB2 DB1 DB0

DDDD

← Lower order bit →

• Read data to CG RAM

RS R/W

Code 1 0

DB7 DB6 DB5 DB4

∗ ∗ ∗D

← Higher order bit →

DB3 DB2 DB1 DB0

DDDD

← Lower order bit →

∗=Don’t Care

Read Data to CG RAM or DD RAM instruction is executed when the code ”1” is written into (RS)

and (R/W).

By the execution of this instruction, the binary 5-bit data “DDDDD” are read out from CG RAM,

and the binary 8-bit data “DDDDDDDD” are read out from DD RAM. The selection of the CG

RAM or DD RAM is determined by the previous instruction.

Before executing this instruction, either the CG RAM address set or DD RAM address set must

be executed, otherwise the first read out data Invalidated.

When this instruction is serially executed, the next address data is normally read from the second

read.

The address set instruction is not required if the cursor shift instruction is executed just

beforehand (only DD RAM reading).

The cursor shift instruction has same function as the DD RAM address set, so that after reading

the DD RAM, the address increment or decrement is executed automatically according to the entry

mode.

But display shift does not occur regardless of the entry mode.

Note) The address counter (AC) is automatically incremented by 1 after write instructions to either of the CG

RAM or DD RAM. Even if the read instruction is executed after this instruction, the addressed data

can not be read out correctly.

For a correct data read out, either the address set instruction or cursor shift instruction (only with DD

RAM) must be implemented just before this instruction or from the second time read out instruction

execution if the read out instruction is executed 2 times consecutively.

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