NJU6635CH 데이터 시트보기 (PDF) - Japan Radio Corporation

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NJU6635CH

16-CHARACTER 2-LINE DOT MATRIX LCD CONTROLLER DRIVER

Japan Radio Corporation  

NJU6635

i) Set DD RAM Address

RS R/W DB7 DB6 DB5 DB4

Code 0 0 1 A A A

← Higher order bit →

DB3 DB2 DB1 DB0

AAAA

← Lower order bit →

Set DD RAM address instruction is executed when the code “1” is written into DB7 and the

address is written into DB6 to DB0 as shown above.

The address data mentioned by binary code “AAAAAAA “ is written into the address counter (AC)

together with the DD RAM addressing condition. After this instruction, the data writing/reading is

performed into/from the DD RAM.

The DD RAM address is indicated as follows, which is available for DD RAM address only.

Normal mode condition

DD RAM 1-Line

DD RAM 2-Line (Addressing mode 1)

DD RAM 2-Line (Addressing mode 2)

DD RAM address

: (00)H – (0F)H

: (10)H – (1F)H

: (40)H – (4F)H

Double height size display condition

DD RAM 1-Line

DD RAM address

: (00)H – (0F)H

j) Read Busy Flag & Address

RS R/W DB7 DB6 DB5 DB4

Code 0 1 BF A A A

← Higher order bit →

DB3 DB2 DB1 DB0

AAAA

← Lower order bit →

This instruction reads out the internal status of the NJU6635. When this instruction is executed,

the busy flag (BF) which indicates the internal operation, is read out from DB7 and the address of

CG RAM or DD RAM is read out from DB6 to DB0 (an address for CG RAM or DD RAM is

determined by the previous instruction).

(BF)=1 indicates that internal operation is in progress. The next instruction is inhibited when

(BF)=1. Check the (BF) status before the next write operation.

k) Write Data to CG or DD RAM

• Write data to CG RAM

RS R/W DB7 DB6 DB5 DB4

Code 1 0 ∗ ∗ ∗ D

← Higher order bit →

DB3 DB2 DB1 DB0

DDDD

← Lower order bit →

• Write data to DD RAM

RS R/W

Code 1 0

DB7 DB6 DB5 DB4

DDDD

← Higher order bit →

DB3 DB2 DB1 DB0

DDDD

← Lower order bit →

∗=Don’t Care

Write Data to CG RAM or DD RAM instruction is executed when the code ”1” is written into (RS)

and code “0” is written into (R/W).

By the execution of this instruction, the binary 5-bit data “DDDDD” are written into the CG RAM,

and the binary 8-bit data “DDDDDDDD” are written into the DD RAM. The selection of the CG

RAM or DD RAM is determined by the previous instruction.

After this instruction execution, the address increment(+1) or decrement(-1) is performed

automatically according to the entry mode set. And the display shift is also executed according to

the previous entry mode set.

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