NJU6635CH 데이터 시트보기 (PDF) - Japan Radio Corporation

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NJU6635CH

16-CHARACTER 2-LINE DOT MATRIX LCD CONTROLLER DRIVER

Japan Radio Corporation  

NJU6635

(3) Instructions

The NJU6635 incorporates two resisters, which are Instruction Register (IR) and a Data Register (DR).

These two registers store control information temporarily to allow interface between NJU6635 and MPU or

peripheral ICs operating different cycles. The operation of NJU6635 is determined by this control signal

from MPU. The control information includes register selection signals (RS), read/write signals (R/W) and

data bus signals (DB0 to DB7).

Table 5. Shows each instruction and its operating time.

Note) The execution time mentioned in Table 5. is based on fcp or fOSC=540kHz.

If the oscillation frequency is changed, the execution time is also changed.

Table 5. Table of Instruction

INSTRUCTION

Maker Test

Clear Display

Return Home

/ Font Size Set

CODE

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0000000000

0000000001

000000001E

DESCRIPTION

EXEC TIME

(fOSC=540kHz)*

All “0” code is using for maker

testing.

–

Display clear and sets DD

RAM address 0 in AC.

315.9µs

Sets DD RAM address 0 In AC

and returns display being

shifted to original position.

DD RAM contents remain

18.5µs

unchanged.

Entry Mode Set

0

Display ON/OFF

Control

0

Cursor or Display

Shift

0

Function Set

0

Set CG RAM

Address 0

Set DD RAM

Address 0

Read Busy

Flag & Address 0

Write Data to CG or

DD or MK RAM

1

Sets cursor move direction and

species shift of display are

0

0

0

0

0

0

1

I/D S

performed In data read/write.

I/D=1:Increment,

I/D=D:Decrement,S=1:Accopa

nies display shift.

Sets of display On/Off(D),

0 0 0 0 0 1 D C B cursor On/Off(C) and blink of

cursor position character(B)

Move cursor and shifts display

without changing DD RAM

contents.

0 0 0 0 1 S/C R/L ∗ ∗ S/C=1 : Display shift

S/C=0 : Cursor shift

R/L=1 : Shift to right

R/L=0 : Shift to the left

Sets interface data length(DL),

Display address mode(A)

DL=1 : 8 bits, DL=0 : 4 bits

A=0 : Addressing mode 1

A=1 : Addressing mode 2

0 0 0 1 DL A ∗ M1 M0 M1=0 : 32-Character 1-Line

M1=1 : 16-Character 2-Line

M0=0 : Pin configuration

mode A

M0=1 : Pin configuration

mode B

001∗

CG RAM address

Sets CG RAM address. After

this instruction, the data is

transferred on CG RAM.

01

DD RAM address

Sets DD RAM address. After

this instruction, the data is

transferred on DD RAM.

1 BF

∗∗

AC

AC

Read busy flag and AC

contents.

BF=1 : Internally operating

BF=0 : Can accept instruction

0

Write Data(DD RAM)

Writes data into CG or DD

RAM.

∗∗∗

(CG RAM)

18.6µs

18.6µs

28µs

18.6µs

18.6µs

18.5µs

0µs

18.6µs

Read Data from CG

or DD or MK RAM 1 1

Read Data(DD RAM)

∗∗∗

(CG RAM)

Reads data from CG or DD

RAM

28µs

Explanation of

Abbreviation

DD RAM : Display data RAM, CG RAM : Character generator RAM

ACG : CG RAM address, ADD : DD RAM address, Corresponds to cursor address

AC : Address counter used for both DD and CG RAM

∗=Don’t Care

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