NJU3101 데이터 시트보기 (PDF) - Japan Radio Corporation

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NJU3101

4-BIT SINGLE CHIP TINY CONTROLLER

Japan Radio Corporation  

NJU3101

s BLOCK DIAGRAM

STACK

TLUaddr PC

MUX

ROM

512 x 8 bits

IR

ID

CPU CORE

X-Reg Y-Reg

AC

X’-Reg Y’-Reg

ALU

RAM

16 x 4 bits

CPU

TIMING

GENERATOR

STANDBY

CONTROLLER

OSC

VDD

VSS

TEST

RESET

OSC1

OSC2

PORTA

PORTB

PORTC

PORTD

PORTE

-2-

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