ADSP-21MSP58BST-104 데이터 시트보기 (PDF) - Analog Devices
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ADSP-21MSP58BST-104 Datasheet PDF : 40 Pages
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ADSP-21msp58/59
CLOCK OR
CRYSTAL
ANALOG
INPUT
ANALOG
OUTPUT
HIP CONTROL
HIP DATA/ADDR
12
3
44
5
3 78
CLKIN XTAL VCC GNDA
VDD GND HOST HIP
MODE
CLKOUT
RESET
SERIAL
PORT 0
IRQ2
BR
ADSP-21msp58/59
BG
MMAP
FL0
SERIAL
PORT 1
PMS
RD WR ADDRESS DATA DMS BMS
SCLK
RFS
TFS
DT
DR
SCLK
RFS OR IRQ0
TFS OR IRQ1
DT OR FO
DR OR FI
14
24
HOST
PROCESSOR
(OPTIONAL)
SERIAL DEVICE
(OPTIONAL)
SERIAL DEVICE
(OPTIONAL)
D23-22
24
D23-8
14
2 D15-8
16
8
A D CS
OE
WE
PROGRAM
MEMORY
(OPTIONAL)
A
OE
D CS
WE DATA
MEMORY &
PERIPHERALS
(OPTIONAL)
A
D CS
OE BOOT
MEMORY
e.g., EPROM
27C64
27C128
27C256
27C512
NOTE: The two MSBs of the Boot EPROM Address are also the two MSBs of the Data Bus.
This is only for the 27C256 and 27C512.
Figure 3. ADSP-21msp58/59 Basic System Configuration
CLKOUT signal is enabled and disabled by the CLKODIS bit
in the SPORT0 Autobuffer Control Register, DM[0x3FF3].
Because the ADSP-21msp58/59 includes an on-chip oscillator
circuit, an external crystal may also be used. The crystal should
be connected across the CLKIN and XTAL pins, with two ca-
pacitors connected as shown in Figure 4. A parallel-resonant,
fundamental frequency, microprocessor-grade crystal should be
used.
CLKIN
XTAL
ADSP-21msp58/59
CLKOUT
Figure 4. External Crystal Connections
Reset
The RESET signal initiates a master reset of the ADSP-
21msp58/59. The RESET signal must be asserted during the
power-up sequence to assure proper initialization. RESET dur-
ing initial power-up must be held long enough to allow the
processor’s internal clock to stabilize. If RESET is asserted at
any time after power-up, the clock continues to run and does
not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is ap-
plied to the processor and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles will ensure that the PLL has locked (this
does not, however, include the crystal oscillator start-up time).
During this power-up sequence, the RESET signal should be
held low. On any subsequent resets, the RESET signal must
meet the minimum pulse width specification, tRSP.
The RESET input contains some hysteresis; however, if you use
an RC circuit to generate your RESET signal, the use of an ex-
ternal Schmidt trigger is recommended.
The master RESET sets all internal stack pointers to the empty
stack condition, masks all interrupts, and clears the MSTAT
register. When RESET is released, if there is no pending bus re-
quest and the chip is configured for booting (MMAP = 0), the
boot loading sequence is performed. Then the first instruction is
fetched from internal program memory location 0x0000 and ex-
ecution begins.
Program Memory Interface
The on-chip program memory address bus (PMA) and on-chip
program memory data bus (PMD) are multiplexed with the on-
chip data memory buses (DMA, DMD), creating a single exter-
nal data bus and a single external address bus. The data and
address busses are three-stated when the DSP runs from inter-
nal memory. Refer to the ADSP-2100 Family User’s Manual,
Chapter 10, “Memory Interface” for a detailed explanation. The
14-bit address bus directly addresses up to 16K words. See
“Program Memory Maps” for details on program memory
addressing.
The program memory data lines are bidirectional. The program
memory select (PMS) signal indicates access to program
memory and can be used as a chip select signal. The write (WR)
signal indicates a write operation and is used as a write strobe.
–6–
REV. 0
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