ADSP-21MSP58BST-104 데이터 시트보기 (PDF) - Analog Devices
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ADSP-21MSP58BST-104 Datasheet PDF : 40 Pages
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ADSP-21msp58/59
Autobuffering
In some applications, it is advantageous to perform block data
transfers between the analog converters and processor memory.
Analog interface autobuffering enables the automatic transfer of
data blocks directly from the ADC to on-chip processor data
memory or from on-chip processor data memory directly to the
DAC.
ADC and DAC Interrupts
The analog interface generates two interrupts that signal either:
(1) a 16-bit, 8 kHz analog-to-digital or digital-to-analog conver-
sion has been completed, or (2) an autobuffer block transfer
has been completed (i.e., the data buffer contents have been
received or transferred).
When an analog interrupt occurs, the processor vectors to the
addresses listed in Table II, Interrupt Priority & Interrupt Vector
Addresses.
The ADC receive and DAC transmit interrupts occur at an
8 kHz rate, indicating when the data registers should be ac-
cessed. On the receive side, the ADC interrupt is generated each
time an A/D conversion cycle is completed and the 16-bit data
word is available in the ADC receive register. On the transmit
side, the DAC interrupt is generated each time an D/A conver-
sion cycle is completed and the DAC transmit register is ready
for the next 16-bit data word.
Both interrupts are generated simultaneously at an 8 kHz rate,
occurring every 3250 instruction cycles with a 13 MHz internal
processor clock. The interrupts are generated continuously,
starting when the analog interface is powered up by setting the
APWD bits (Bits 5 and 6) to one in the analog control register.
Because both interrupts occur simultaneously, only one should
be enabled (in IMASK) to vector to a single service routine that
handles transmit and receive data. However, when using
autobuffer transfers, both interrupts should be enabled.
ADSP-21msp58/59 REGISTERS
Figure 9 summarizes the ADSP-21msp58/59 registers. Some
registers store values. For example, AX0 stores an ALU oper-
and; I4 stores a DAG2 pointer. Other registers consist of control
bits and fields, or status flags. For example ASTAT contains
status flags from arithmetic operations, and fields in DWAIT
control the number of wait states for different zones of data
memory.
A secondary set of registers in all computational units allows a
single-cycle context switch.
The bit and field definitions for control and status registers are
given in the rest of this section, except IMASK, ICNTL, and
IFC, which are defined earlier in this data sheet. The system
control register, DWAIT register, timer registers, HIP control
registers, HIP data registers, and SPORT control registers are
all mapped into data memory locations; that is, you access these
registers by reading and writing data memory locations rather
than register names. The particular data memory address is
shown with each memory-mapped register.
Register bit values shown on the following pages are the default
bit values after reset. If no values are shown, the bits are indeter-
minate at reset. Reserved bits are shown in gray; these bits
should always be written with zeros.
DAG 1
I0 M0 L0
I1 M1 L1
I2 M2 L2
I3 M3 L3
DAG 2
I4 M4 L4
I5 M5 L5
I6 M6 L6
I7 M7 L7
PROGRAM SEQUENCER
SSTAT
CNTR
OWRCNTR
COUNT
STACK
4 x 14
ICNTL
IFC
IMASK
MSTAT
ASTAT
STATUS
STACK
12 x 25
LOOP
STACK
4 x 18
PC
STACK
16 x 14
0x3FFF SYSTEM CONTROL
0x3FFE DM WAIT CONTROL
14 PMA BUS
PROGRAM
SRAM
2K x 24
PROGRAM
ROM
4K x 24
ADSP-21msp59
ONLY
DATA
SRAM
2K x 16
14 DMA BUS
24 PMD BUS
PX
16 DMD BUS
HOST
INTERFACE
PORT
0x3FE0-0x3FE5 DATA
0x3FE6-0x3FE7 STATUS
0x3FE8
HMASK
AX0 AX1 AY0 AY1
ALU
AR AF
MX0 MX1 MY0 MY1
MAC
MR0 MR1 MR2 MF
SI SE SB
SHIFTER
SR0 SR1
0x3FEC 0x3FED
DAC
ADC
0x3FEE-0x3FEF
CONTROL REGISTERS
ANALOG INTERFACE
RX0 TX0
0x3FFA-0x3FF3
CONTROL REGISTERS
SPORT 0
RX1 TX1
0x3FF2-0x3FEF
CONTROL REGISTERS
SPORT 1
TIMER
0x3FFD TPERIOD
0x3FFC TCOUNT
0x3FFB TSCALE
FLAG
POWERDOWN
CONTROL
LOGIC
Figure 9. ADSP-21msp58/59 Registers
REV. 0
–11–
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