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HEF4071BP

Quad 2-input OR gate

NXP Semiconductors. 

NXP Semiconductors

HEF4071B

Quad 2-input OR gate

6. Functional description

Table 3.

Input

nA

L

L

H

H

Function table[1]

nB

L

H

L

H

[1] H = HIGH voltage level; L = LOW voltage level.

7. Limiting values

Output

nY

L

H

H

H

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).

Symbol Parameter

Conditions

Min

Max

Unit

VDD

supply voltage

IIK

input clamping current

VI

input voltage

IOK

output clamping current

II/O

input/output current

VI < 0.5 V or VI > VDD + 0.5 V

VO < 0.5 V or VO > VDD + 0.5 V

−0.5

+18

V

-

±10

mA

−0.5

VDD + 0.5 V

-

±10

mA

-

±10

mA

IDD

Tstg

Tamb

Ptot

supply current

storage temperature

ambient temperature

total power dissipation

Tamb = −40 °C to + 125 °C

DIP14

-

50

mA

−65

+150

°C

−40

+125

°C

[1] -

750

mW

SO14

[2] -

500

mW

P

power dissipation

per output

-

100

mW

[1] For DIP14 packages: above Tamb = 70 °C, Ptot derates linearly with 12 mW/K.

[2] For SO14 packages: above Tamb = 70 °C, Ptot derates linearly with 8 mW/K.

8. Recommended operating conditions

Table 5.

Symbol

VDD

VI

Tamb

∆t/∆V

Recommended operating conditions

Parameter

Conditions

supply voltage

input voltage

ambient temperature

in free air

input transition rise and fall rate

VDD = 5 V

VDD = 10 V

VDD = 15 V

Min Max

Unit

3

15

V

0

VDD

V

−40

+125

°C

-

3.75

ns/V

-

0.5

ns/V

-

0.08

ns/V

HEF4071B_4

Product data sheet

Rev. 04 — 28 November 2008

© NXP B.V. 2008. All rights reserved.

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