SST89E52RC 데이터 시트보기 (PDF) - Silicon Storage Technology
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SST89E52RC Datasheet PDF : 57 Pages
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FlashFlex MCU
SST89E52RC / SST89E54RC
SuperFlash Command Register (SFCM)
Location
7
B2H
-
6
FCM6
5
FCM5
4
FCM4
3
FCM3
2
FCM2
1
FCM1
Data Sheet
0
FCM0
Reset Value
00H
Symbol
-
FCM[6:0]
Function
Reserved
Flash operation command
000_0001b Chip-Erase
000_1011b Sector-Erase
000_1101b Partition0-Erase
000_1100b Byte-Verify1
000_1110b Byte-Program
000_0011b Secure-Page
Page-Level Security Commands
SFAH=90H; Secure-Page0
SFAH=91H; Secure-Page1
SFAH=92H; Secure-Page2
SFAH=93H; Secure-Page3
SFAH=94H; Secure-Page4
000-0101b Secure-Chip
Chip-Level Security Commands
SFAH=B0H; Disable-Extern-IAP
SFAH=B1H; Disable-Extern-Boot
SFAH=B2H; Disable-Extern-MOVC
SFAH=B3H; Disable-Extern-Host-Cmd
000-1000b Boot Options
Boot Option Setting Commands
SFAH=E0H; Enable-Clock-Double
SFAH=E1H; Boot-From-User-Vector
SFAH=E2H; Boot-From-Zero
000-1001b Set-User-Boot-Vector
All other combinations are not implemented, and reserved for future use.
1. Byte-Verify has a single machine cycle latency and will not generate any INT1# interrupt regardless of FIE.
SuperFlash Address Registers (SFAL)
Location
7
6
5
4
3
2
1
B3H
SuperFlash Low Order Byte Address Register
0
Reset Value
00H
Symbol
SFAL
Function
Mailbox register for interfacing with flash memory block. (Low order address register).
SuperFlash Address Registers (SFAH)
Location
7
B4H
6
5
4
3
2
1
SuperFlash High Order Byte Address Register
0
Reset Value
00H
Symbol
SFAH
Function
Mailbox register for interfacing with flash memory block. (High order address register).
©2007 Silicon Storage Technology, Inc.
17
S71259-04-000
1/07
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