SST89E52RC 데이터 시트보기 (PDF) - Silicon Storage Technology

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SST89E52RC

FlashFlex MCU

Silicon Storage Technology 

FlashFlex MCU

SST89E52RC / SST89E54RC

Data Sheet

Auxiliary Register (AUXR)

Location

7

6

5

4

3

2

1

0

Reset Value

8EH

-

-

-

-

-

-

EXTRAM

AO

xxxxxx10b

Symbol

EXTRAM

AO

Function

Internal/External RAM access

0: Internal Expanded RAM access within range of 00H to FFH using MOVX @Ri /

@DPTR. Beyond 100H, the MCU always accesses external data memory.

For details, refer to Section 3.3, “Expanded Data RAM Addressing” .

1: External data memory access.

Disable/Enable ALE

0: ALE is emitted at a constant rate of 1/3 the oscillator frequency in 6 clock mode, 1/6 fOSC in

12 clock mode.

1: ALE is active only during a MOVX or MOVC instruction.

Auxiliary Register 1 (AUXR1)

Location

7

6

5

A2H

-

-

-

4

3

2

-

GF2

0

1

0

Reset Value

-

DPS

xxxx00x0b

Symbol

GF2

DPS

Function

General purpose user-defined flag

DPTR registers select bit

0: DPTR0 is selected.

1: DPTR1 is selected.

Sequence Register 0 (SFIS0)

Location

7

6

5

4

3

2

1

0

Reset Value

97H

(Write only)

N/A

Symbol

SFIS0

Function

Register used with SFIS1 to provide a feed sequence to validate writing

to WDTC and SFCM. Without a proper feed sequence, writing to SFCM will be ignored

and writing to WDTC in Watchdog mode will cause an immediate Watchdog reset.

Sequence Register 1 (SFIS1)

Location

7

6

5

4

3

2

1

0

Reset Value

C4H

(Write only)

N/A

Symbol

SFIS1

Function

Register used with SFIS0 to provide a feed sequence to validate writing

to WDTC and SFCM.

©2007 Silicon Storage Technology, Inc.

21

S71259-04-000

1/07

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