PCK2014A 데이터 시트보기 (PDF) - Philips Electronics

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PCK2014A

CK98 (100/133 MHz) spread spectrum system clock generator

Philips Electronics 

Philips Semiconductors

CK98 (100/133 MHz) spread spectrum

system clock generator

FEATURES

• ESD classification testing is done to JEDEC Standard JESD22.

Protection exceeds 2000 V to HBM per method A114.

• Latch-up testing is done to JEDEC Standard JESD78

which exceeds 100 mA.

• Mixed 2.5 V and 3.3 V operation

• Six CPU clocks at 2.5 V

• Six PCI clocks at 3.3 V, one free-running

(synchronous with CPU clocks)

• Two 3.3 V fixed clocks @ 66 MHz

• Three 2.5 V IOAPIC clocks @ 16.67 MHz

• One 3.3 V 48 MHz USB clock

• Two 3.3 V reference clocks @ 14.318 MHz

• Reference 14.31818 MHz Xtal oscillator input

• 133 MHz or 100 MHz operation

• Power management control input pins

• CPU clock jitter ≤ 150 ps cycle-cycle

• CPU clock skew ≤ 175 ps pin-pin

• 0.0 ns – 1.5 ns CPU - 3V66 delay

• 1.5 ns – 3.5 ns 3V66 - PCI delay

• 1.5 ns – 4.0 ns CPU - IOAPIC delay

• 1.5 ns – 4.0 ns CPU - PCI delay

• Available in 56-pin SSOP package

• ±0.6% Center spread spectrum capability via select pins

• –0.6% Down spread spectrum capability via select pins

DESCRIPTION

The PCK2014A is a clock generator (frequency synthesizer) chip for

a Pentium III and other similar processors.

The PCK2014A has six CPU clock outputs at 2.5 V, two 3V66 clocks

running at 66 MHz. there are six PCI clock outputs running at

33 MHz. Additionally, the part has three 2.5 V IOAPIC clock outputs

at 16.67 MHz and two 3.3 V reference clock outputs at 14.318 MHz.

All clock outputs meet Intel’s drive strength, rise/fall time, jitter,

accuracy, and skew requirements.

The part possesses dedicated power-down, CPUSTOP, and

PCISTOP input pins for power management control. These inputs

are synchronized on-chip and ensure glitch-free output transitions.

When the CPUSTOP input is asserted, the CPU clock outputs and

3V66 clock outputs are driven LOW. When the PCISTOP input is

asserted, the PCI clock outputs are driven LOW.

Finally, when the PWRDWN input pin is asserted, the internal

reference oscillator and PLLs are shut down, and all outputs are

driven LOW.

PIN CONFIGURATION

VSS 1

REF0 2

REF1 3

VDD3V 4

XTAL_IN 5

XTAL_OUT 6

VSS 7

VSS 8

PCI_F 9

VDD3V 10

PCI_1 11

PCI_2 12

VSS 13

PCI_3 14

PCI_4 15

VDD3V 16

VDD3V 17

PCI_5 18

VSS 19

VSS 20

VSS 21

VDD3V 22

VDD3V 23

VSS 24

3V66_0 25

3V66_1 26

VDD3V 27

SEL133/100 28

ORDERING INFORMATION

PACKAGES

56-pin plastic SSOP

TEMPERATURE RANGE

0 to +70 °C

ORDER CODE

PCK2014ADL

Intel and Pentium are registered trademarks of Intel Corporation.

2001 Apr 02

2

Product specification

PCK2014A

56 VDD25V

55 APIC2

54 APIC1

53 APIC0

52 VSS

51 VDD25V

50 CPUCLK5

49 CPUCLK4

48 VSS

47 VDD25V

46 CPUCLK3

45 CPUCLK2

44 VSS

43 VDD25V

42 CPUCLK1

41 CPUCLK0

40 VSS

39 VDD3V

38 VSS

37 PCISTOP

36 CPUSTOP

35 PWRDWN

34 SPREAD

33 SEL1

32 SEL0

31 VDD3V

30 48MHz_USB

29 VSS

SW00879

DRAWING NUMBER

SOT371-1

853–2245 25964

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