NCP1336A/B
ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted)
Symbol
Rating
Min
Typ
Max Unit
SUPPLY SECTION
VCCon
VCCmin
VCCreset
ICC1
ICC1light
VCC increasing level at which the current source turns−off
VCC level below which output pulses are stopped
Internal latch reset level
Internal IC consumption, no output load on DRV pin (Fsw = 10 kHz)
ICC1 for a Feedback Voltage Equal to VHVCO (internal bias reduction), with CT =
220 pF (corresponding to an Fsw of about 20 kHz)
14
15
16
V
8
9
10
V
−
5.5
−
V
−
1.4
2.0
mA
1.8
mA
ICC2 Internal IC consumption, 1 nF output load on pin 9, Fsw = 65 kHz
−
2.5
3.0
mA
ICC3 Internal IC consumption, hiccup phase (VCCmin < VCC < VCCon)
INTERNAL STARTUP CURRENT SOURCE (TJ > 05C) (HV Pin Biased to 60 Vdc)
IC2
High−voltage current source, VCC = 10 V (Note 3)
IC1
High−voltage current source, VCC = 0
VTh
VCC transition level for IC1 to IC2 toggling point (IHV = 2.5 mA)
Ileak
Leakage current for the high voltage source, VHV(pin) = 500 Vdc
DRIVE OUTPUT
−
0.45
0.6
mA
3
6
9
mA
150
300
550
mA
0.3
0.7
0.9
V
1
12
30
mA
Tr
Tf
Isource
Isink
VDRVlow
Output voltage rise−time @ CL = 1 nF, 10%−90% of a 12 V output signal
Output voltage fall−time @ CL = 1 nF, 10%−90% of a 12 V output signal
Source current capability at VDRV = 2 V
Sink current capability at VDRV = 10 V
DRV pin level at VCC close to VCCmin with a 33 kW resistor to GND and a 1 nF
capacitor to GND
−
40
75
ns
−
25
60
ns
−
500
−
mA
−
800
−
mA
7.6
−
−
V
VDRVhigh DRV pin level at VCC = 28 V with a 1 nF capacitor to GND (Note 3)
DEMAGNETIZATION INPUT
−
−
17
V
Vth
Input threshold voltage (VZCD(pin) decreasing)
VH
Hysteresis (VZCD(pin) increasing)
VCH
VCL
Input clamp voltage
High state (IZCD(pin) = 3.0 mA)
Low state (IZCD(pin) = −2.0 mA)
Tdem
Demag propagation delay (VZCD(pin) decreasing from 4 V to −0.3 V)
Cpar
Internal input capacitance at VZCD(pin) = 1 V
Tblank Blanking Delay after tON
Tout
Timeout after last demag transition
CURRENT COMPARATOR
35
55
90
mV
15
35
55
mV
8
10
12
V
−0.9 −0.7
0
V
−
150
250
ns
−
10
−
pF
2
3
4
ms
4
5.25
6.5
ms
IIB
Input Bias Current @ 1 V input level on CS pin
−
0.02
−
mA
ILimit1 Maximum internal current setpoint – TJ = 25°C – OPP pin grounded
0.76
0.8
0.84
V
ILimit2 Maximum internal current setpoint – TJ from −40°C to 125°C – OPP pin grounded 0.744
0.8
0.856
V
Ipeak_VCO Percentage of maximum peak current level at which VCO takes over (Note 4)
22
25
28
%
TDEL Propagation delay from current detection to gate OFF state
−
100
160
ns
TLEB
Leading Edge Blanking Duration
TJ = −5°C to +125°C
TJ = −40°C to +125°C
240
295
350
ns
240
295
360
3. Minimum value for TJ = 125°C.
4. The peak current setpoint goes down as the load decreases. It is frozen below Ipeak_VCO (Ipeak = cst)
5. If negative voltage in excess to −300 mV is applied to OPP pin, the current setpoint decrease is no longer guaranteed to be linear.
6. NTC on OTP pin with R = 8.8 kW at 110°C.
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