NCP1336 데이터 시트보기 (PDF) - ON Semiconductor

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NCP1336

Quasi-Resonant Current Mode Controller for High Power Universal Off-Line Supplies

ON Semiconductor 

NCP1336A/B

The first startup period is calculated by the formula, CV

= It which implies a 22 mF x 0.9 V / 150 mA = 132 ms startup

time for the first sequence. The second sequence is obtained

by changing I to 3 mA (worst case calculation) with DV =

15 V − 0.9 V = 14.1 V, which finally leads to a second startup

time of 22 mF x 14.1 V / 3 mA = 103 ms. The total startup

time becomes 103 ms + 132 ms = 235 ms. Please note that

this calculation is approximated by the presence of the knee

in the vicinity of the transition.

As soon as VCC reaches VCCon, drive pulses are delivered

on pin 9 and the auxiliary winding increases the voltage on

the VCC pin. At the same time, the controller smoothly

ramps up the peak current to Imax (0.8 V / Rsense) which is

reached after a typical 5 ms soft−start period. As soon as the

CS voltage reaches 0.8 V = ILimit1, the internal error flag

IpFlag is asserted. When the error flag is asserted, the current

source on pin 3 is activated and charges up the capacitor

connected to this pin. If the error flag is still asserted when

the timer capacitor has reached the threshold level

VtimFault, then the controller assumes that the power

supply has really undergone a fault condition and

immediately stops all pulses to enter a safe burst operation.

Figure 5 depicts the VCC evolution during a proper startup

sequence, showing the state of the error flag:

Figure 5. An error flag gets asserted as soon as the current setpoint reaches its upper limit

(0.8 V/Rsense). Here the timer lasts 50 ms, a 100 nF capacitor being connected to pin 3.

NCP1336 Operation

The valley detection is done by monitoring the voltage of

the auxiliary winding of the transformer. The typical

detection level is fixed at 55 mV. When a valley is detected,

the decimal counter is incremented. The operating valley

(1st, 2nd, 3rd or 4th) is determined by the FB voltage. As FB

voltage decreases or increases, the valley comparators

toggle one after another to select the proper valley. The

activation of an “n” valley comparator disables the “n+1” or

“n−1” valley comparator (depending if FB increases or

decreases) and enables the corresponding “n” output of the

decimal counter. Figure 6 shows the internal arrangement of

the valley selection circuitry.

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