MT8941B 데이터 시트보기 (PDF) - Mitel Networks

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MT8941B

CMOS ST-BUS™ FAMILY Advanced T1/CEPT Digital Trunk PLL

Mitel Networks 

CMOS MT8941B

oscillators of DPLL #1 and DPLL #2 to have

maximum tolerances of ±32ppm and ±50ppm

respectively.

However, if DPLL #1 and DPLL #2 are daisy-chained

as shown in Figures 9 and 10, the output clock

tolerance of DPLL #1 will be equal to that of the

DPLL #2 oscillator when DPLL #2 is free-running. In

this case, the oscillator tolerance of DPLL #1 has no

impact on its output clock tolerance. For this reason,

a) Distributed Timing

Data Bus

it is recommended to use a ±32 ppm oscillator for

DPLL #2 and a ±100 ppm oscillator for DPLL #1.

Differences between MT8941B and

MT8940

The MT8941B and MT8940 are pin and mode

compatible for most applications. However, the user

should take note of the following differences between

the two parts.

8 kHz Reference Signal

Line Card 1

M

U

X

8 kHz Reference Signal

MT8940

Clocks

Line Card n

MT8940

Clocks

b) Centralized Timing

8 kHz Reference Signal

M

U

X

MT8941B

Clocks

8 kHz Reference Signal

Data Bus

Line Card 1

Line Card n

Figure 8 - Application Differences between the MT8940 and MT8941B

9

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