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MT8941B

CMOS ST-BUS™ FAMILY Advanced T1/CEPT Digital Trunk PLL

Mitel Networks 

CMOS MT8941B

Pin Description (continued)

Pin #

Name

DIP PLCC

Description

13 15

C4b Clock 4.096 MHz- Bidirectional (TTL compatible input and Totem-pole output) - When

the mode select bit MS3 (pin 17) is HIGH, it provides the 4.096 MHz clock output with the

falling edge in the frame pulse (F0b) window. When pin 17 is LOW, C4b is an input to an

external clock at 4.096 MHz.

14 16

C2o Clock 2.048 MHz (Three state output) - This is the divide by two output of C4b (pin 13) and

has a falling edge in the frame pulse (F0b) window. The high impedance state of this output

is controlled by ENC2o (pin 16).

15 17

C2o Clock 2.048 MHz (Three state output) - This is the divide by two output of C4b (pin 13) and

has a rising edge in the frame pulse (F0b) window. The high impedance state of this output is

controlled by ENC2o (pin 16).

16 19 ENC2o Enable 2.048 MHz clock (TTL compatible input) - This active high input enables both C2o

and C2o outputs (pins 14 and 15). When LOW, these outputs are in high impedance

condition.

17 20 MS3 Mode select 3 input (TTL compatible) - This input in conjunction with MS2 (pin 7) selects

the minor mode of operation for DPLL #2. (Refer to Table 3.)

18, 21, Ai, Bi Inputs A and B (TTL compatible) -These are the two inputs of the uncommitted NAND

19 22

gate.

20 23

21 24

Yo Output Y (Totem pole output) - Output of the uncommitted NAND gate.

CVb Variable clock Bidirectional (TTL compatible input and Totem-pole output) - When

acting as an output (MS1-LOW) during the NORMAL mode of DPLL #1, this pin provides the

1.544 MHz clock locked to the input frame pulse F0i (pin 5). When MS1 is HIGH, it is an

input to an external clock at 1.544 MHz or 2.048 MHz to provide the internal signal at 8 kHz

to DPLL #2.

22 26

23 27

CV

RST

Variable clock (Three state output) - This is the inverse output of the signal appearing on

pin 21, the high impedance state of which is controlled by ENCV (pin 1).

Reset (Schmitt trigger input) - This input (active LOW) puts the MT8941B in its reset state.

To guarantee proper operation, the device must be reset after power-up. The time constant

for a power-up reset circuit (see Figures 9-13) must be a minimum of five times the rise time

of the power supply. In normal operation, the RST pin must be held low for a minimum of

60nsec to reset the device.

24 28

4,

5,

18,

25

VDD VDD (+5V) Power supply.

NC No Connection.

3

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