MC145540 데이터 시트보기 (PDF) - Motorola => Freescale

부품명

상세내역

일치하는 목록

MC145540

ADPCM Codec

Motorola => Freescale 

The implementation of Long Frame Sync for this device has maintained industry compatibility and been

optimized for external clocking simplicity. The PCM data output goes low impedance with the rising

edge of the FST pin but the MSB of the data is clocked out due to the logical AND of the transmit frame

sync (FST pin) with the transmit data clock (BCLKT pin). This allows either the rising edge of the FST

enable or the rising edge of the BCLKT data clock to be first. This implementation includes the PCM

data output remaining low impedance until the middle of the LSB (seven and a half data clock cycles for

64 kbps PCM, three and a half data clock cycles for 32 kbps ADPCM, etc.). This allows the frame sync

to be approximately rising edge aligned with the initiation of the PCM data word transfer but the frame

sync does not have a precise timing requirement for the end of the PCM data word transfer. This pre-

vents bus contention between similar devices on a common bus. The device recognizes Long Frame

Sync clocking when the frame sync is held high for two consecutive falling edges of the transmit data

clock.

In the full duplex speech mode, the DSP services one encode interrupt and one decode interrupt per

frame (125 µs). The encode algorithm (i.e., 16 kbps, 24 kbps, or 32 kbps ADPCM, or 64 kbps PCM) is

determined by the length of the transmit output enable at the FST pin. The length of the FST enable

measured in transmit data clock (BCLKT) cycles tells the device which encoding rate to use. This en-

able length information is used by the encoder each frame. The transmit ADPCM word corresponding to

this request will be computed during the next frame and be available a total of two frames after being

requested. This transmit enable length information can be delayed by the device an additional four

frames corresponding to a total of six frames. This six frames of delay allows the device to be clocked

with the same clocks for both transmit (encode) and receive (decode), and to be frame aligned for

applications that require every sixth frame signaling. It is important to note that the enable length in-

formation is delayed and not the actual ADPCM (PCM) sample word. The amount of delay for the FST

enable length is controlled by the SCP port at BR7 (b5). The digital data output circuitry counts BCLKT

cycles to keep the data output (DT pin) low impedance for the duration of the ADPCM data word (2, 3, 4,

or 8 BCLKT cycles) minus one half of a BCLKT cycle.

The length of the FST enable tells the DSP what encoding algorithm to use. The transmit logic decides

on each frame sync whether it should interpret the next frame sync pulse as a Long or a Short Frame

Sync. The device is designed to prevent PCM bus contention by not allowing the PCM data output to go

low impedance for at least two frame sync cycles after power is applied or when coming out of the

power-down mode.

The receive side of the device is designed to accept the same frame sync and data clock as the transmit

side and to be able to latch its own transmit PCM data word. Thus the PCM digital switch only needs to

be able to generate one type of frame sync for use by both transmit or receive sections of the device.

The logical AND of the receive frame sync with the receive data clock tells the device to start latching the

serial word into the receive data input on the falling edges of the receive data clock. The internal receive

logic counts the receive data clock falling edges while the FSR enable is high and transfers the enable

length and the PCM data word into internal registers for access by the DSP machine which also sets the

DSP’s decoder interrupt.

The receive digital section of this device accepts serial ADPCM (PCM) words at the DR pin under the

control of the BCLKR and FSR pins. The FSR enable duration measured in BCLKR cycles, tells the

device which decode algorithm (i.e., 16 kbps, 24 kbps, or 32 kbps ADPCM, or 64 kbps PCM) the DSP

machine should use for the word that is being received at the DR pin. This algorithm may be changed on

a frame by frame basis.

When the device is programmed to be in the PCM Codec mode by BR0 (4:3), the device will output and

input the complete 8-bit PCM words using the long frame sync clocking format as though the FST and

FSR pulses were held high for eight data clock cycles.

The DSP machine receives an interrupt when an ADPCM word has been received and is waiting to be

decoded into a PCM word. The DSP machine performs a decode and an encode every frame when the

device is operating in its full duplex conversation mode. The DSP machine decodes the ADPCM word

according to CCITT G.726 for 32 kbps, 24 kbps, and 16 kbps.

MOTOROLA

MC145540

2-9

Share Link: