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MC145540

ADPCM Codec

Motorola => Freescale 

2.4 PIN DESCRIPTIONS

The pin descriptions are listed in functional groups and provide detailed information about the particular

subsystem of the device and the associated pins.

2.4.1 Power Supply Pins

VSS

Negative Power Supply (Pin 22)

This is the most negative power supply and is typically connected to 0 V.

VEXT

External Power Supply Input (Pin 9)

This power supply input pin must be between 2.7 and 5.25 V. Internally, it is connected to the input of the

VDSP voltage regulator, the 5 V regulated charge pump, and all digital I/O including the Serial Control

Port and the ADPCM Serial Data Port. This pin is also connected to the analog output drivers (PO +,

PO –, AXO + and AXO –). This pin should be decoupled to VSS with a 0.1 µF ceramic capacitor. This pin

is internally connected to the VDD and VDSP pins when the device is powered down.

VDSP

Digital Signal Processor Power Supply Output (Pin 8)

This pin is connected to the output of the on-chip VDSP voltage regulator which supplies the positive

voltage to the DSP circuitry and to the other digital blocks of the ADPCM Codec. This pin should be

decoupled to VSS with a 0.1 µF ceramic capacitor. This pin cannot be used for powering external loads.

This pin is internally connected to the VEXT pin during power down to retain memory.

VDD

Positive Power Supply Input/Output (Pin 28)

This is the positive output of the on-chip voltage regulated charge pump and the positive power supply

input to the analog sections of the device. Depending on the supply voltage available, this pin can

function in one of two different operating modes.

When VEXT is supplied from a regulated 5 V ±5% power supply, VDD is an input and should be externally

connected to VEXT. Charge pump capacitor C1 should not be used and the charge pump should be

disabled in BR0 (b2). In this case VEXT and VDD can share the same 0.1 µF ceramic decoupling capaci-

tor to VSS.

When VEXT is supplied from 2.70 to 5.25 V, such as battery powered applications, the charge pump

should be used. In this case VDD is the output of the on-chip voltage regulated charge pump and must

not be connected to VEXT. VDD should be decoupled to VSS with a 1.0 µF ceramic capacitor. This pin

cannot be used for powering external loads in this operating mode. This pin is internally connected to

the VEXT pin when the charge pump is turned off or the device is powered down.

VAG

Analog Ground Output (Pin 4)

This output pin provides a mid-supply analog ground regulated to 2.4 V. All analog signal processing

within this device is referenced to this pin. This pin should be decoupled to VSS with a 0.01 to 0.1 µF

ceramic capacitor. If the audio signals to be processed are referenced to VSS, then special precautions

must be utilized to avoid noise between VSS and the VAG pin. Refer to the applications information in this

document for more information. The VAG pin becomes high impedance when in analog power-down

mode.

C1–, C1+

Charge Pump Capacitor Pins (Pin 23 and 24)

These are the capacitor connections to the internal voltage regulated charge pump that generate the

VDD supply voltage. A 0.1 µF capacitor should be placed between these pins. Note that if an external

VDD is supplied, this capacitor should not be in the circuit.

MOTOROLA

MC145540

2-11

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