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MC145540

ADPCM Codec

Motorola => Freescale 

with adjustable gain which is capable of driving a 300 Ω load to +12 dBm when VEXT is 5 V. The PO +

and PO – outputs are intended to drive loads differentially and not to VSS or VAG. The PO + and PO –

power amplifiers may be powered down independently of the rest of the chip by connecting the PI pin to

VDD or in BR2 (b5).

The other paired power driver outputs are the AXO + and AXO – Auxiliary outputs. These push-pull

output amplifiers are intended to drive a ringer or loud speaker with impedance as low as 300 Ω to

+12 dBm when VEXT is 5 V. The AXO + and AXO – outputs are intended to drive loads differentially and

not to VSS or VAG. The AXO + and AXO – power amplifiers may be powered down independently of the

rest of the chip via the SCP port in BR2 (b6).

2.2.3 Sidetone

The Sidetone function of this device allows a controlled amount of the output from the transmit filter to be

v summed with the output of the DAC at the input to the receive low-pass filter. The sidetone component

has gains of –8.5 dB, –10.5 dB, –12.0 dB, –13.5 dB, –15.0 dB, –18.0 dB, –21.5 dB, and –70 dB. The

sidetone function is controlled by the SCP port in BR1 (b6:b4).

2.2.4

Universal Tone Generator

The Universal Dual Tone Generator function supports both the transmit and the receive sides of this

device. When the tone generator is being used, the decoder function of the DSP circuit is disabled. The

output of the tone generator is made available to the input of the receive digital gain function for use at

the receive analog outputs. In handset applications, this could be used for generating DTMF, distinctive

ringing or call progress feedback signals. In telephone line interface applications, this tone generator

could be used for signaling on the line. The tone generator output is also available for the input to the

encoder function of the DSP machine for outputting at the DT pin. This function is useful in handset

applications for non-network signaling such as information services, answering machine control, etc. At

the network interface side of a cordless telephone application, this function could be used for dialing

feedback or call progress to the handset. The tone generator function is controlled by the SCP port in

BR4, BR5, and BR7. The tone generator does not work when the device is operated in 64 kbps mode,

except when analog loopback is enabled at BR0 (b5). For more information on programming the tone

generators, see Section 8.

2.2.5

Power Down

There are two methods of putting all of this device into a low power consumption mode that makes the

device nonfunctional and consumes virtually no power. PDI/RESET is the power down input and reset

pin which, when taken low for 10 SPC clock cycles or more, powers down the device. Another way to

power the device down is by the SCP port at BR0. BR0 allows the analog section of this device to be

powered down individually and/or the digital section of this device to be powered down individually.

When the chip is powered down, the VAG, TG, RO, PO +, PO –, AXO +, AXO –, DT, and SCP Tx outputs

are high impedance . To return the chip to the power up state, PDI/RESET must be high and the SPC

clock and the FST or the FSR frame sync pulses must be present. The ADPCM algorithm is reset to the

CCITT initial state following the reset transition from low-to-high logic states. The DT output will remain

in a high-impedance state for at least two FST pulses after power up.

2.2.6 Signal Processing Clock (SPC)

This is the clock that sequences the DSP circuit. This clock may be asynchronous to all other functions

of this device. Clock frequencies of 20.48 MHz or 20.736 MHz are recommended. This clock is also

used to drive a digitally phase locked prescaler that is referenced to FST (8 kHz) and automatically

determines the proper divide ratio to use for achieving the required 256 kHz internal sequencing clock

for all analog signal processing, including analog-to-digital conversion, digital-to-analog conversion,

transmit filtering, receive filtering, and analog gain functions of this device and the charge pump.

The SPC input accepts an input clock frequency from 20.48 to 23.04 MHz. This clock frequency should

be a multiple of 256 kHz within a tolerance of ± 10 SPC clock cycles per FST rising edge. For an FST of

8 kHz without jitter, this equates to a tolerance of ± 80 kHz. The total tolerance is measured in SPC

MOTOROLA

MC145540

2-7

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