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M37640E8FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Mitsumi 

Ver 1.4

MITSUBISHI MICROCOMPUTERS

7640 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

1.20 SPECIAL COUNT SOURCE GENERATOR

This device has a built-in special count source genera-

tor. It cons ists of two 8-bit timers: SCSG1, and

SCSG2 (see Figure 1.49). The contents of the timer

latch, corresponding to each timer, determine the di-

vide ratio. The timers can be written to at any time.

The output of the special count source generator can

be a clock source for Timer X, SIO and the two

UARTs.

1.20.1 SCSG Operation

The SCSG1 and SCSG2 are both down count timers.

When the count of a timer reaches 0016, an underflow

occurs at the next count pulse and the contents of the

corresponding timer reload latch are loaded into the

timer. For the count operation for SCSG1 with the

Data Write Mode set to write to the latch only (see

Figure 1.50).

A memory map and the initial values after reset of the

timers and timer reload latches are detailed above.

The divide ratio of each timer is given by 1/(n + 1),

where n is the value written to the timer. The output of

the first timer (SCSG1) is effectively ANDed with the

original clock (F) to provide a count source for the

second timer (SCSG2). This results in a count source

of n/(n + 1) being fed to SCSG2.

The output of the SCSG is a clock, SCSGCLK. The

frequency is calculated as follows:

SCSGCLK = B• SCSG1 • 1

SCSC1+1 SCSG2+1

where SCSG1 is the value written to SCSG1 and

SCSG2 is the value written to SCSG2.

See Figure 1.51 for the Special Count Source Mode

Register.

SCSGM1

SCSGM3

Φ

SCSGM1

SCSG1 Reload Latch (8)

SCSG1 (8)

SCSGM0

SCSGM1

SCSGM3

SCSGM3

SCSGCLK

(To UARTs, Timer X and SIO)

SCSG2 Reload Latch (8)

SCSG (8)

SCSGM2

Fig. 1.49. SCSG Block Diagram

Count Source

SCSG1 Contents

1 0 n n-1

1 0 m m-1

SCSG1 Underflow

SCSG1 Latch Contents

n

m

SCSG1 reload latch contents loaded int SCSG1

Fig. 1.50. Timer Count Operation for SCSG1

MSB

7

Reserved

Reserved Reserved

Reser ved

SCSGM3

SCSGM2

SCSGM1

SCSGM0

LSB

0

Address: 002F16

Access: R/W

Reset: 0016

SCSGM0

SCSGM1

SCSGM2

SCSGM3

Bits 4-7

SCSG1 Data Write Control Bit (bit 0)

0 : Write data in latch and timer

1 : Write data in latch only

SCSG1 Count Stop Bit (bit 1)

0 : Count start

1 : Count stop

SCSG2 Data Write Control Bit (bit 2)

0 : Write data in latch an timer

1 : Write data in latch only

SCSGCLK Output Control Bit (bit 3)

0 : SCSGCLK output disabled (SCSG1 and SCSG2 off)

1 : SCSGCLK output enable.

Reserved (Read/Write “0”)

Fig. 1.51. Special Count Source Mode Register (SCSM)

49

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