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M37640E8FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Mitsumi 

Ver 1.4

MITSUBISHI MICROCOMPUTERS

7640 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

1.19.3 UART Status Register (UxSTS)

The UART Status Register (UxSTS) reflects both the

transmit and receive status (see Figure 1.44). The sta-

tus register is read only. The MSB is always “0” during

a read operation. Writing to this register has no effect.

Status flags are set and reset under the conditions in-

dicated below. The setting and resetting of the

transmit and receive status are not affected by trans-

mit and receive enable flags. The setting and resetting

of the receive error flags and receive buffer full flag dif-

fers when UART address mode is enabled. These

differences are described in section “1.19.7 UART Ad-

dress Mode”.

1.19.3.1 Receive Error Sum Flag

The Receive Error Sum Flag (SER) is set when an

overrun, framing, or parity error occurs after comple-

tion of a receive operation.

It is reset when the status register is read, the hard-

ware reset is asserted, or the receiver is initialized by

setting the Receive Initialization Bit (RIN). If the receive

operation completes while the status register is being

read, the status information is updated upon comple-

tion of the status register read.

1.19.3.2 Receive Overrun Flag

The Receive Overrun Flag (OER) is set if the previous

data in the low-order byte of the receive buffer

(UxTRB1) is not read before the current receive opera-

tion is completed. It is also set if a receive error

occurred for the previous data and the status register

is not read before the current receive operation is com-

pleted. This flag is reset when the status register is

read. This flag is also reset when the hardware reset is

asserted or the receiver is initialized by RIN. If the re-

ceive operation completes while the status register is

being read, the status information is updated upon

completion of the status register read.

1.19.3.3 Receive Framing Error Flag

The Receive Framing Error Flag (FER) is set when the

stop bit of the received data is “0”. If the Stop Bit Se-

lection Bit (STB, bit 3 of UxMOD) is set, the flag is set

if either of the two stop bits is a “0”. This flag is reset

when the status register is read, the hardware reset is

asserted, or the receiver is initialized by RIN. If the re-

ceive operation completes while the status register is

being read, the status information is updated upon

completion of the status register read.

1.19.3.4 Receive Parity Error Flag

The Receive Parity Error Flag (PER) is set when the

parity of received data and the Parity Selection Bit

(PMD, bit 4 of UxMOD) are different. It is enabled only

if the Parity Enable Bit (PEN, bit 5 of UxMOD) is set.

This flag is reset when the status register is read, the

hardware reset is asserted, or the receiver is initialized

by RIN. If the receive operation completes while the

status register is being read, the status information is

updated upon completion of the status register read.

1.19.3.5 Receive Buffer Full Flag

The Receive Buffer Full Flag (RBF) is set when the

last stop bit of the data is received. It is not set when

a receive error occurs. This flag is reset when the low-

order byte of the receive buffer (UxTRB1) is read, the

hardware reset is asserted, or the receive process is

initialized by RIN. If the receive operation completes

while the status register is being read, the status infor-

mation is updated upon completion of the status

register read.

1.19.3.6 Transmission Complete Flag

In the case where no data is contained in the transmit

buffer, the Transmission Complete Flag (TCM) is set

when the last bit in the transmit shift register is trans-

mitted. In the case where the transmit buffer does

contain data, the TCM flag is set when the last bit in

the transmit shift register is transmitted if TBE is a “0”

or CTS handshaking is enabled and CTSx is “1”. The

TCM flag is also set when the hardware reset is as-

serted or when the transmitter is initialized by setting

the Transmit Initialization Bit (TIN, bit 2 of UxCON). It

is reset when a transmission operation begins.

1.19.3.7 Transmission Buffer Empty Flag

The Transmission Buffer Empty Flag (TBE) is set

when the contents of the transmit buffer are loaded

into the transmit shift register. The TBE flag is also

set when the hardware reset is asserted or when the

transmitter is initialized by TIN. It is reset when a write

operation is performed to the low-order byte of the

transmit buffer (UxTRB1).

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