K9F2G08Q0M 데이터 시트보기 (PDF) - Samsung
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K9F2G08Q0M Datasheet PDF : 38 Pages
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K9F2G08Q0M K9F2G16Q0M
K9F2G08U0M K9F2G16U0M
Preliminary
FLASH MEMORY
Figure 1-2. K9F2G16X0M (X16) Functional Block Diagram
VCC
VSS
A11 - A27
X-Buffers
Latches
& Decoders
2048M + 64M Bit
NAND Flash
ARRAY
A0 - A10
Y-Buffers
Latches
& Decoders
Command
Command
Register
(1024 + 32)Word x 131072
Data Register & S/A
Cache Register
Y-Gating
I/O Buffers & Latches
CE
Control Logic
RE
& High Voltage
WE
Generator
Global Buffers
Output
Driver
CLE ALE PRE WP
VCC
VSS
I/0 0
I/0 15
Figure 2-2. K9F2G16X0M (X16) Array Organization
1 Block = 64 Pages
(64K + 2k) Word
128K Pages
(=2,048 Blocks)
1K Words
32 Words
1 Page = (1K + 32)Words
1 Block = (1K + 32)Word x 64 Pages
= (64K + 2K) Words
1 Device = (1K+32)Word x 64Pages x 2048 Blocks
= 2112 Mbits
16 bit
Page Register
1K Words
I/O 0 ~ I/O 15
32 Words
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6
1st Cycle
A0
A1
A2
A3
A4
A5
A6
2nd Cycle A8
A9
A10
*L
*L
*L
*L
3rd Cycle A11
A12
A13
A14
A15
A16
A17
4th Cycle A19
A20
A21
A22
A23
A24
A25
5th Cycle A27
*L
*L
*L
*L
*L
*L
NOTE : Column Address : Starting Address of the Register.
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
I/O 7
A7
*L
A18
A26
*L
I/O8 ~ 15
*L
*L
*L
*L
*L
Column Address
Column Address
Row Address
Row Address
Row Address
7
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