ISPLSI2032A-80LT44I 데이터 시트보기 (PDF) - Lattice Semiconductor

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ISPLSI2032A-80LT44I

In-System Programmable High Density PLD

Lattice Semiconductor 

ispLSI 2032/A Timing Model

Specifications ispLSI 2032/A

I/O Cell

GRP

GLB

ORP

I/O Cell

Feedback

Ded. In

I/O Pin

(Input)

#21

I/O Delay

#20

Reset

GRP

#22

#45

Comb 4 PT Bypass #23

Reg 4 PT Bypass

#24

GLB Reg Bypass

#28

20 PT

XOR Delays

#25, 26, 27

GLB Reg

Delay

D

Q

RST

#29, 30,

31, 32

Control RE

ORP Bypass

S #37

ORP

N Delay

DESIG #36

#38,

39

I/O Pin

(Output)

Y0,1,2

GOE 0

#43, 44

#42

PTs

OE

#33, 34, CK

35

NEW

#40, 41

0491/2000

R Derivations of tsu, th and tco from the Product Term Clock1

O tsu

= Logic + Reg su - Clock (min)

F = (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min))

= (#20+ #22+ #26) + (#29) - (#20+ #22+ #35)

E 2.1 ns = (0.6 + 0.7 + 4.1) + (0.5) - (0.6 + 0.7 + 2.5)

2 th

= Clock (max) + Reg h - Logic

3 = (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)

= (#20+ #22+ #35) + (#30) - (#20+ #22+ #26)

0 1.5 ns = (0.6 + 0.7 + 3.8) + (1.8) - (0.6 + 0.7 + 4.1)

2 tco

= Clock (max) + Reg co + Output

I = (tio + tgrp + tptck(max)) + (tgco) + (torp + tob)

S = (#20+ #22+ #35) + (#31) + (#36 + #38)

L 7.7 ns = (0.6 + 0.7 + 3.8) + (0.7) + (0.7 + 1.2)

isp Note: Calculations are based upon timing specifications for the ispLSI 2032/A-180L

USE

Table 2- 0042-16/2032

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